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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-02 14:42:11 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-06-02 14:42:11 +0000 |
commit | 7a869e70367757ca322cdec534504881f11ec731 (patch) | |
tree | 1a359dd14e4a2588c5cdcfc9a9dbce3451edb679 /llvm/lib/Target | |
parent | ffb4d2bff7f1024aa3accd1c387017003b8ce94d (diff) | |
download | bcm5719-llvm-7a869e70367757ca322cdec534504881f11ec731.tar.gz bcm5719-llvm-7a869e70367757ca322cdec534504881f11ec731.zip |
[DAGCombine] Fold insert_subvector(bitcast(x),bitcast(y),c1) -> bitcast(insert_subvector(x,y),c2)
Move this combine from x86 into generic DAGCombine, which currently only manages cases where the bitcast is between types of the same scalarsize.
Differential Revision: https://reviews.llvm.org/D59188
llvm-svn: 362324
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 253f4487976..5bdcb89b8f5 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -43066,42 +43066,6 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG, } } - // Push subvector bitcasts to the output, adjusting the index as we go. - // insert_subvector(bitcast(v), bitcast(s), c1) -> - // bitcast(insert_subvector(v,s,c2)) - // TODO: Move this to generic - which only supports same scalar sizes. - if ((Vec.isUndef() || Vec.getOpcode() == ISD::BITCAST) && - SubVec.getOpcode() == ISD::BITCAST) { - SDValue VecSrc = peekThroughBitcasts(Vec); - SDValue SubVecSrc = peekThroughBitcasts(SubVec); - MVT VecSrcSVT = VecSrc.getSimpleValueType().getScalarType(); - MVT SubVecSrcSVT = SubVecSrc.getSimpleValueType().getScalarType(); - if (Vec.isUndef() || VecSrcSVT == SubVecSrcSVT) { - MVT NewOpVT; - SDValue NewIdx; - unsigned NumElts = OpVT.getVectorNumElements(); - unsigned EltSizeInBits = OpVT.getScalarSizeInBits(); - if ((EltSizeInBits % SubVecSrcSVT.getSizeInBits()) == 0) { - unsigned Scale = EltSizeInBits / SubVecSrcSVT.getSizeInBits(); - NewOpVT = MVT::getVectorVT(SubVecSrcSVT, NumElts * Scale); - NewIdx = DAG.getIntPtrConstant(IdxVal * Scale, dl); - } else if ((SubVecSrcSVT.getSizeInBits() % EltSizeInBits) == 0) { - unsigned Scale = SubVecSrcSVT.getSizeInBits() / EltSizeInBits; - if ((IdxVal % Scale) == 0) { - NewOpVT = MVT::getVectorVT(SubVecSrcSVT, NumElts / Scale); - NewIdx = DAG.getIntPtrConstant(IdxVal / Scale, dl); - } - } - if (NewIdx && DAG.getTargetLoweringInfo().isOperationLegal( - ISD::INSERT_SUBVECTOR, NewOpVT)) { - SDValue Res = DAG.getBitcast(NewOpVT, VecSrc); - Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewOpVT, Res, SubVecSrc, - NewIdx); - return DAG.getBitcast(OpVT, Res); - } - } - } - // Match concat_vector style patterns. SmallVector<SDValue, 2> SubVectorOps; if (collectConcatOps(N, SubVectorOps)) |