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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2019-05-07 09:19:09 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2019-05-07 09:19:09 +0000 |
| commit | 79ea85c6afb56534e77adb908e9f553c319f30c0 (patch) | |
| tree | bf671c93ac769c9dba0387c84ec636b05c5e5794 /llvm/lib/Target | |
| parent | fdbb61856e84d69194d848e6d492193326eb60f4 (diff) | |
| download | bcm5719-llvm-79ea85c6afb56534e77adb908e9f553c319f30c0.tar.gz bcm5719-llvm-79ea85c6afb56534e77adb908e9f553c319f30c0.zip | |
AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand
Summary:
No test case because I don't know of a way to trigger this, but I
accidentally caused this to fail while working on a different change.
Change-Id: I8015aa447fe27163cc4e4902205a203bd44bf7e3
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61490
llvm-svn: 360123
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 8f4a073839d..1e77d63ba9d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -3191,6 +3191,24 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, } } + if (isSOP2(MI) || isSOPC(MI)) { + const MachineOperand &Src0 = MI.getOperand(Src0Idx); + const MachineOperand &Src1 = MI.getOperand(Src1Idx); + unsigned Immediates = 0; + + if (!Src0.isReg() && + !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType)) + Immediates++; + if (!Src1.isReg() && + !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType)) + Immediates++; + + if (Immediates > 1) { + ErrInfo = "SOP2/SOPC instruction requires too many immediate constants"; + return false; + } + } + if (isSOPK(MI)) { auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16); if (Desc.isBranch()) { |
