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authorDuncan Sands <baldrick@free.fr>2011-03-15 08:41:24 +0000
committerDuncan Sands <baldrick@free.fr>2011-03-15 08:41:24 +0000
commit7921ac09756e74c0bfe9c5ddd38182a3766d20f0 (patch)
treea9dda40c7601f2eedfcc8d272e1a7c85b295ccf1 /llvm/lib/Target
parent0b8cdfb6ec1f0e7ee031161989844d6db89c1174 (diff)
downloadbcm5719-llvm-7921ac09756e74c0bfe9c5ddd38182a3766d20f0.tar.gz
bcm5719-llvm-7921ac09756e74c0bfe9c5ddd38182a3766d20f0.zip
Avoid a compiler warning about reg possibly being used uninitialized
when building with assertions disabled. llvm-svn: 127675
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/PTX/PTXISelLowering.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/PTX/PTXISelLowering.cpp b/llvm/lib/Target/PTX/PTXISelLowering.cpp
index 147b2a82cfc..1b4b7e6625d 100644
--- a/llvm/lib/Target/PTX/PTXISelLowering.cpp
+++ b/llvm/lib/Target/PTX/PTXISelLowering.cpp
@@ -212,11 +212,9 @@ SDValue PTXTargetLowering::
else if (Outs[0].VT == MVT::f32) {
reg = PTX::F0;
}
- else if (Outs[0].VT == MVT::f64) {
- reg = PTX::FD0;
- }
else {
- assert(false && "Can return only basic types");
+ assert(Outs[0].VT == MVT::f64 && "Can return only basic types");
+ reg = PTX::FD0;
}
MachineFunction &MF = DAG.getMachineFunction();
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