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authorMomchil Velikov <momchil.velikov@arm.com>2019-11-01 15:01:36 +0000
committerMomchil Velikov <momchil.velikov@arm.com>2019-11-01 15:01:53 +0000
commit7849862f46933306454342b0e8ee05e4e6806646 (patch)
tree315f56f2980da44bf705f70dbfb57e875b7fb6cb /llvm/lib/Target
parent5a7ae6321ebededd5a5e8c8c331ea54cc30c4198 (diff)
downloadbcm5719-llvm-7849862f46933306454342b0e8ee05e4e6806646.tar.gz
bcm5719-llvm-7849862f46933306454342b0e8ee05e4e6806646.zip
[AArch64] Output the pseudo SPACE in asm and object files
Summary: It outputs nothing, but is useful for writing tests, checking asm output. Reviewers: t.p.northover, ostannard, tellenbach Reviewed By: tellenbach Subscribers: tellenbach, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69185 Change-Id: I6b58310e9e5632f0976d2000ce975ee28df90ebe
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp6
-rw-r--r--llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp8
2 files changed, 12 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 1a16468484a..00d80319a83 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -282,6 +282,12 @@ void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
return;
}
+ if (Opcode == AArch64::SPACE) {
+ O << '\t' << MAI.getCommentString() << " SPACE";
+ printAnnotation(O, Annot);
+ return;
+ }
+
// Instruction TSB is specified as a one operand instruction, but 'csync' is
// not encoded, so for printing it is treated as a special case here:
if (Opcode == AArch64::TSB) {
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index 8cb7a167298..8f4d9cb94d6 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -601,8 +601,12 @@ void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
return;
- } else if (MI.getOpcode() == AArch64::CompilerBarrier) {
- // This just prevents the compiler from reordering accesses, no actual code.
+ }
+
+ if (MI.getOpcode() == AArch64::CompilerBarrier ||
+ MI.getOpcode() == AArch64::SPACE) {
+ // CompilerBarrier just prevents the compiler from reordering accesses, and
+ // SPACE just increases basic block size, in both cases no actual code.
return;
}
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