diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-03 00:26:02 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-03 00:26:02 +0000 |
| commit | 7828331329a85cd872117ed482689599dee2322d (patch) | |
| tree | 91cfe00f027a00c9ebc642b09ae409b53fc3b517 /llvm/lib/Target | |
| parent | 15fd6ac4ba75d161d008e4e44bcdbcb6f528dd93 (diff) | |
| download | bcm5719-llvm-7828331329a85cd872117ed482689599dee2322d.tar.gz bcm5719-llvm-7828331329a85cd872117ed482689599dee2322d.zip | |
[mips] Set flag isAsCheapAsAMove flag on instruction LUi.
llvm-svn: 167345
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 3f6cebdc18d..3319553935e 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -421,7 +421,7 @@ class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, // Load Upper Imediate class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: FI<op, (outs RC:$rt), (ins Imm:$imm16), - !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> { + !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { let rs = 0; let neverHasSideEffects = 1; let isReMaterializable = 1; |
