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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-13 20:44:23 +0000 |
---|---|---|
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-13 20:44:23 +0000 |
commit | 7784992999aba8c254df9a250d11d4fec256912a (patch) | |
tree | def466f2411b0a6677ca25be342261420d5a5655 /llvm/lib/Target | |
parent | 1a179e821947e4ef516058a1ec0de570f58cda74 (diff) | |
download | bcm5719-llvm-7784992999aba8c254df9a250d11d4fec256912a.tar.gz bcm5719-llvm-7784992999aba8c254df9a250d11d4fec256912a.zip |
R600/SI: Use s_movk_i32
llvm-svn: 221922
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.td | 4 | ||||
-rw-r--r-- | llvm/lib/Target/R600/SILowerControlFlow.cpp | 2 | ||||
-rw-r--r-- | llvm/lib/Target/R600/SIShrinkInstructions.cpp | 13 |
3 files changed, 17 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 6e098cd1dc1..b84a2b12149 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -368,12 +368,12 @@ class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL> : SOPC_Helper<op, SSrc_64, i64, opName, cond>; class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK < - op, (outs SReg_32:$dst), (ins i16imm:$src0), + op, (outs SReg_32:$dst), (ins u16imm:$src0), opName#" $dst, $src0", pattern >; class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK < - op, (outs SReg_64:$dst), (ins i16imm:$src0), + op, (outs SReg_64:$dst), (ins u16imm:$src0), opName#" $dst, $src0", pattern >; diff --git a/llvm/lib/Target/R600/SILowerControlFlow.cpp b/llvm/lib/Target/R600/SILowerControlFlow.cpp index 59270ee062e..9702565c462 100644 --- a/llvm/lib/Target/R600/SILowerControlFlow.cpp +++ b/llvm/lib/Target/R600/SILowerControlFlow.cpp @@ -586,6 +586,8 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { MachineBasicBlock::iterator Start = MBB.getFirstNonPHI(); const MCInstrDesc &SMovK = TII->get(AMDGPU::S_MOVK_I32); + assert(isInt<16>(StackOffset) && isInt<16>(StackSizeBytes)); + BuildMI(MBB, Start, NoDL, SMovK, AMDGPU::FLAT_SCR_LO) .addImm(StackOffset); diff --git a/llvm/lib/Target/R600/SIShrinkInstructions.cpp b/llvm/lib/Target/R600/SIShrinkInstructions.cpp index 0b9e7ca9666..45e83f54e7c 100644 --- a/llvm/lib/Target/R600/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/R600/SIShrinkInstructions.cpp @@ -189,6 +189,19 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { Next = std::next(I); MachineInstr &MI = *I; + // Try to use S_MOVK_I32, which will save 4 bytes for small immediates. + if (MI.getOpcode() == AMDGPU::S_MOV_B32) { + const MachineOperand &Src = MI.getOperand(1); + + // TODO: Handle FPImm? + if (Src.isImm()) { + if (isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src)) { + MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); + continue; + } + } + } + if (!TII->hasVALU32BitEncoding(MI.getOpcode())) continue; |