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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-15 14:42:36 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-15 14:42:36 +0000 |
| commit | 750082d1fe306405c6b3350ce84c4b9c446eb5c3 (patch) | |
| tree | 5d0dd93610a7757e648a6b75af9ca3abbd7e1550 /llvm/lib/Target | |
| parent | 38c67a27fe811074d39aaba6d4e9fbcc8f0640fc (diff) | |
| download | bcm5719-llvm-750082d1fe306405c6b3350ce84c4b9c446eb5c3.tar.gz bcm5719-llvm-750082d1fe306405c6b3350ce84c4b9c446eb5c3.zip | |
AMDGPU/SI: Fix regression with no-return atomics
Summary:
In the added test-case, the atomic instruction feeds into a non-machine
CopyToReg node which hasn't been selected yet, so guard against
non-machine opcodes here.
Reviewers: arsenm, tstellarAMD
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19043
llvm-svn: 266433
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 34fa7391744..8cd3fd72de2 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3046,6 +3046,7 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, // special case to check if the atomic has only one extract_subreg use, // which itself has no uses. if ((Node->hasNUsesOfValue(1, 0) && + Node->use_begin()->isMachineOpcode() && Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG && !Node->use_begin()->hasAnyUseOfValue(0))) { unsigned Def = MI->getOperand(0).getReg(); |
