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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-28 20:54:52 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-28 20:54:52 +0000 |
| commit | 73aa8f687a17d7dd6a870cae4325c589fd038809 (patch) | |
| tree | 5d542a1de689b1933d3100381991238f6a993a7d /llvm/lib/Target | |
| parent | e5d042cd562a690d781a652ce70fc4568ba772c5 (diff) | |
| download | bcm5719-llvm-73aa8f687a17d7dd6a870cae4325c589fd038809.tar.gz bcm5719-llvm-73aa8f687a17d7dd6a870cae4325c589fd038809.zip | |
AMDGPU: Fix splitting x16 SMRD loads
When used recursively, this would set the kill flag
on the intermediate step from first splitting
x16 to x8.
llvm-svn: 248741
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 432f763d9cb..5d0cfb32e4c 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2037,8 +2037,8 @@ void SIInstrInfo::splitSMRD(MachineInstr *MI, .addOperand(*SOff); unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR) - .addOperand(*SOff) - .addImm(HalfSize); + .addReg(SOff->getReg(), 0, SOff->getSubReg()) + .addImm(HalfSize); Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi) .addReg(SBase->getReg(), getKillRegState(IsKill), SBase->getSubReg()) |
