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| author | Evan Cheng <evan.cheng@apple.com> | 2010-09-08 22:57:08 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-08 22:57:08 +0000 |
| commit | 722cd122dcb87a5330b72085e21881f985259ab5 (patch) | |
| tree | 778a99980a94d6e66fced6d6e58d4838d2f63ac9 /llvm/lib/Target | |
| parent | a42039d5eb4acc8555ace318014b59bc3887dd0f (diff) | |
| download | bcm5719-llvm-722cd122dcb87a5330b72085e21881f985259ab5.tar.gz bcm5719-llvm-722cd122dcb87a5330b72085e21881f985259ab5.zip | |
Fix LDM_RET schedule itinery.
llvm-svn: 113435
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSchedule.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA8.td | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA9.td | 6 |
5 files changed, 19 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index e66f9b9ad0a..372277858ce 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -940,7 +940,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1 in def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), - IndexModeUpd, LdStMulFrm, IIC_Br, + IndexModeUpd, LdStMulFrm, IIC_iLoadmBr, "ldm${addr:submode}${p}\t$addr!, $dsts", "$addr.addr = $wb", []>; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 096a8c7350e..5f88fbe8a2e 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -2454,7 +2454,8 @@ let Defs = let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1 in def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, - reglist:$dsts, variable_ops), IIC_Br, + reglist:$dsts, variable_ops), + IIC_iLoadmBr, "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", "$addr.addr = $wb", []> { let Inst{31-27} = 0b11101; diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td index b60ccca4686..75667215777 100644 --- a/llvm/lib/Target/ARM/ARMSchedule.td +++ b/llvm/lib/Target/ARM/ARMSchedule.td @@ -43,6 +43,7 @@ def IIC_iLoadiu : InstrItinClass; def IIC_iLoadru : InstrItinClass; def IIC_iLoadsiu : InstrItinClass; def IIC_iLoadm : InstrItinClass; +def IIC_iLoadmBr : InstrItinClass; def IIC_iStorei : InstrItinClass; def IIC_iStorer : InstrItinClass; def IIC_iStoresi : InstrItinClass; diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td index 282abca9880..2902fbbad0f 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA8.td +++ b/llvm/lib/Target/ARM/ARMScheduleA8.td @@ -122,6 +122,15 @@ def CortexA8Itineraries : ProcessorItineraries< InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0]>]>, + // + // Load multiple plus branch + InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>, + InstrStage<2, [A8_Pipe0], 0>, + InstrStage<2, [A8_Pipe1]>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_LdSt0]>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, + // Integer store pipeline // // use A8_Issue to enforce the 1 load/store per cycle limit diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td index df2f896a8d4..4a764cc8117 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA9.td +++ b/llvm/lib/Target/ARM/ARMScheduleA9.td @@ -107,6 +107,12 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData<IIC_iLoadm , [InstrStage<1, [A9_Pipe1]>, InstrStage<1, [A9_LSPipe]>]>, + // + // Load multiple plus branch + InstrItinData<IIC_iLoadmBr , [InstrStage<1, [A9_Pipe1]>, + InstrStage<1, [A9_LSPipe]>, + InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>, + // Integer store pipeline /// // Immediate offset |
