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| author | Pirama Arumuga Nainar <pirama@google.com> | 2016-01-22 01:16:57 +0000 |
|---|---|---|
| committer | Pirama Arumuga Nainar <pirama@google.com> | 2016-01-22 01:16:57 +0000 |
| commit | 71e9a2a4c4a4e08ad98f5c319ed5d1704ce1537f (patch) | |
| tree | c89fd518b19a74cf7b7378b452248605cf65d06c /llvm/lib/Target | |
| parent | 4f4815789d8419365c0c60a2ab58fab7a735d096 (diff) | |
| download | bcm5719-llvm-71e9a2a4c4a4e08ad98f5c319ed5d1704ce1537f.tar.gz bcm5719-llvm-71e9a2a4c4a4e08ad98f5c319ed5d1704ce1537f.zip | |
Do not lower VSETCC if operand is an f16 vector
Summary:
SETCC with f16 vectors has OperationAction set to Expand but still gets
lowered to FCM* intrinsics based on its result type. This patch skips
lowering of VSETCC if the operand is an f16 vector.
v4 and v8 tests included.
Reviewers: ab, jmolloy
Subscribers: srhines, llvm-commits
Differential Revision: http://reviews.llvm.org/D15361
llvm-svn: 258471
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2a838d63f0f..c8e67ff8305 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -6689,6 +6689,9 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType()); } + if (LHS.getValueType().getVectorElementType() == MVT::f16) + return SDValue(); + assert(LHS.getValueType().getVectorElementType() == MVT::f32 || LHS.getValueType().getVectorElementType() == MVT::f64); |
