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authorSimon Pilgrim <llvm-dev@redking.me.uk>2017-07-06 15:34:17 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2017-07-06 15:34:17 +0000
commit713600747e93574c1b3ec76d7df5b40e5d19b2e3 (patch)
tree10897ce5eaf306ab905736e39431b411d5bea70f /llvm/lib/Target
parent0c37b19331ca1f5b10463c9a1303b09446d482e8 (diff)
downloadbcm5719-llvm-713600747e93574c1b3ec76d7df5b40e5d19b2e3.tar.gz
bcm5719-llvm-713600747e93574c1b3ec76d7df5b40e5d19b2e3.zip
[X86][SSE4A] Add support for shuffle combining to INSERTQI.
llvm-svn: 307268
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp16
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 60bc5a5c8e0..30353c85ccc 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -27714,6 +27714,22 @@ static bool combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
/*AddTo*/ true);
return true;
}
+
+ if (matchVectorShuffleAsINSERTQ(IntMaskVT, V1, V2, Mask, BitLen, BitIdx)) {
+ if (Depth == 1 && Root.getOpcode() == X86ISD::INSERTQI)
+ return false; // Nothing to do!
+ V1 = DAG.getBitcast(IntMaskVT, V1);
+ DCI.AddToWorklist(V1.getNode());
+ V2 = DAG.getBitcast(IntMaskVT, V2);
+ DCI.AddToWorklist(V2.getNode());
+ Res = DAG.getNode(X86ISD::INSERTQI, DL, IntMaskVT, V1, V2,
+ DAG.getConstant(BitLen, DL, MVT::i8),
+ DAG.getConstant(BitIdx, DL, MVT::i8));
+ DCI.AddToWorklist(Res.getNode());
+ DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Res),
+ /*AddTo*/ true);
+ return true;
+ }
}
// Don't try to re-form single instruction chains under any circumstances now
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