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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-22 21:05:25 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-22 21:05:25 +0000 |
commit | 707780b420621b6c3b4b8e3e17f52634406fdf1b (patch) | |
tree | 97c4b3259dfddd599184824427daf9dc22bad6fa /llvm/lib/Target | |
parent | e9bc0b5a3c7d617b29bcf93df20ba4c77c27fb94 (diff) | |
download | bcm5719-llvm-707780b420621b6c3b4b8e3e17f52634406fdf1b.tar.gz bcm5719-llvm-707780b420621b6c3b4b8e3e17f52634406fdf1b.zip |
AMDGPU: Always allocate emergency stack slot at offset 0
This allows us to ensure that 0 is never a valid pointer
to a user object, and ensures that the offset is always legal
without needing a register to access it. This comes at the cost
of usable offsets and wasted stack space.
llvm-svn: 295877
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 03de4bf508f..80ba15a64a5 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -391,11 +391,25 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized( if (!MFI.hasStackObjects()) return; - assert(RS && "RegScavenger required if spilling"); - int ScavengeFI = MFI.CreateStackObject( - AMDGPU::SGPR_32RegClass.getSize(), - AMDGPU::SGPR_32RegClass.getAlignment(), false); - RS->addScavengingFrameIndex(ScavengeFI); + bool MayNeedScavengingEmergencySlot = MFI.hasStackObjects(); + if (MayNeedScavengingEmergencySlot) { + // We force this to be at offset 0 so no user object ever has 0 as an + // address, so we may use 0 as an invalid pointer value. This is because + // LLVM assumes 0 is an invalid pointer in address space 0. Because alloca + // is required to be address space 0, we are forced to accept this for + // now. Ideally we could have the stack in another address space with 0 as a + // valid pointer, and -1 as the null value. + // + // This will also waste additional space when user stack objects require > 4 + // byte alignment. + // + // The main cost here is losing the offset for addressing modes. However + // this also ensures we shouldn't need a register for the offset when + // emergency scavenging. + int ScavengeFI = MFI.CreateFixedObject( + AMDGPU::SGPR_32RegClass.getSize(), 0, false); + RS->addScavengingFrameIndex(ScavengeFI); + } const SISubtarget &ST = MF.getSubtarget<SISubtarget>(); const SIInstrInfo *TII = ST.getInstrInfo(); |