Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies"

This reverts commit r286171, it breaks piglit test fs-discard-exit-2

llvm-svn: 286530

2 files changed, 5 insertions, 26 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index a4a5de126df..addc8062b29 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -440,7 +440,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
 
   setSchedulingPreference(Sched::RegPressure);
   setJumpIsExpensive(true);
-  setHasMultipleConditionRegisters(true);
 
   // SI at least has hardware support for floating point exceptions, but no way
   // of using or handling them is implemented. They are also optional in OpenCL
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index 3b7db8c465f..9e62980940b 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -121,31 +121,11 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
           }
         }
 
-        // If there are uses which are just a copy back from this new VReg_1
-        // to another SGPR_64 just forward propagate original SGPR_64.
-        SmallVector<MachineInstr *, 4> RegUses;
-        for (auto &Use : MRI.use_instructions(Dst.getReg()))
-          if (Use.isFullCopy())
-            RegUses.push_back(&Use);
-
-        while (!RegUses.empty()) {
-          MachineInstr *Use = RegUses.pop_back_val();
-          if (Use->getOperand(1).getReg() == Dst.getReg()) {
-            unsigned RegCopy = Use->getOperand(0).getReg();
-            if (!TargetRegisterInfo::isVirtualRegister(RegCopy))
-              continue;
-            Use->eraseFromParent();
-            MRI.replaceRegWith(RegCopy, Src.getReg());
-          }
-        }
-
-        if (!MRI.use_empty(Dst.getReg()))
-          BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
-            .addOperand(Dst)
-            .addImm(0)
-            .addImm(-1)
-            .addOperand(Src);
-
+        BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
+          .addOperand(Dst)
+          .addImm(0)
+          .addImm(-1)
+          .addOperand(Src);
         MI.eraseFromParent();
       } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
                  SrcRC == &AMDGPU::VReg_1RegClass) {