summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorBradley Smith <bradley.smith@arm.com>2014-04-09 14:43:50 +0000
committerBradley Smith <bradley.smith@arm.com>2014-04-09 14:43:50 +0000
commit6f1aa59c3118c39b708f2d01e847024e78a166a2 (patch)
treedac3f3218bdb2c3598fe6d5d6822aabc44d3c600 /llvm/lib/Target
parent5511f08055d2311cd217a10584d9eaae8a585803 (diff)
downloadbcm5719-llvm-6f1aa59c3118c39b708f2d01e847024e78a166a2.tar.gz
bcm5719-llvm-6f1aa59c3118c39b708f2d01e847024e78a166a2.zip
[ARM64] Rename FP to the UAL-compliant 'X29'.
llvm-svn: 205884
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM64/ARM64RegisterInfo.td2
-rw-r--r--llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp2
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64RegisterInfo.td b/llvm/lib/Target/ARM64/ARM64RegisterInfo.td
index 96001c54ecb..88093ff84d4 100644
--- a/llvm/lib/Target/ARM64/ARM64RegisterInfo.td
+++ b/llvm/lib/Target/ARM64/ARM64RegisterInfo.td
@@ -112,7 +112,7 @@ def X25 : ARM64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
def X26 : ARM64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
def X27 : ARM64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
def X28 : ARM64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
-def FP : ARM64Reg<29, "fp", [W29]>, DwarfRegAlias<W29>;
+def FP : ARM64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
def LR : ARM64Reg<30, "lr", [W30]>, DwarfRegAlias<W30>;
def SP : ARM64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
def XZR : ARM64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index bff81761fb4..88840883da8 100644
--- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -1871,7 +1871,7 @@ int ARM64AsmParser::tryParseRegister() {
// Also handle a few aliases of registers.
if (RegNum == 0)
RegNum = StringSwitch<unsigned>(lowerCase)
- .Case("x29", ARM64::FP)
+ .Case("fp", ARM64::FP)
.Case("x30", ARM64::LR)
.Case("x31", ARM64::XZR)
.Case("w31", ARM64::WZR)
OpenPOWER on IntegriCloud