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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-01-15 20:44:00 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-01-15 20:44:00 +0000 |
| commit | 6ed996cdf02a1ba6f35cd9b207b66165c71fa9e1 (patch) | |
| tree | ee7e37e1bd177d0b2d6823cd1f619ae2d40cf591 /llvm/lib/Target | |
| parent | a6c1974e0659bf226ddf25c2790ff614c53333b0 (diff) | |
| download | bcm5719-llvm-6ed996cdf02a1ba6f35cd9b207b66165c71fa9e1.tar.gz bcm5719-llvm-6ed996cdf02a1ba6f35cd9b207b66165c71fa9e1.zip | |
[CostModel][X86] Fix AVX512BW vector shift costs for vXi16 types
We already have patterns in place to support 128/256-bit shifts without AVX512VL
llvm-svn: 292077
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index dfc2a8d8c62..567ef743f6b 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -323,6 +323,14 @@ int X86TTIImpl::getArithmeticInstrCost( return LT.first * Entry->Cost; static const CostTblEntry AVX512BWCostTable[] = { + { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw + { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw + { ISD::SRA, MVT::v8i16, 1 }, // vpsravw + + { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw + { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw + { ISD::SRA, MVT::v16i16, 1 }, // vpsravw + { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw { ISD::SRA, MVT::v32i16, 1 }, // vpsravw |
