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| author | Eli Friedman <eli.friedman@gmail.com> | 2009-08-22 03:13:10 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2009-08-22 03:13:10 +0000 |
| commit | 682d8c1881ba5609e79c4402ff8c05f2e7d618e5 (patch) | |
| tree | 0da3df8792fedf1ee56d243040cfcceb09825a84 /llvm/lib/Target | |
| parent | abd97fe1b122cbf4cad9cf0f04d1c27770205ffb (diff) | |
| download | bcm5719-llvm-682d8c1881ba5609e79c4402ff8c05f2e7d618e5.tar.gz bcm5719-llvm-682d8c1881ba5609e79c4402ff8c05f2e7d618e5.zip | |
Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
llvm-svn: 79719
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f04b45dc793..7d8362c93da 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2134,8 +2134,11 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, N->getOperand(0), NegatedCount); } - assert(VT == MVT::i64 && - (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && + // We can get here for a node like i32 = ISD::SHL i32, i64 + if (VT != MVT::i64) + return SDValue(); + + assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!"); // We only lower SRA, SRL of 1 here, all others use generic lowering. |
