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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-01-12 23:13:00 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-01-12 23:13:00 +0000 |
| commit | 64dae8354b11f1ee8e0f894195d648f659b4b515 (patch) | |
| tree | e63a706ed139ec65fbe408aca4b010e12da553af /llvm/lib/Target | |
| parent | b3ff1cbc088f81e18fdddb5e3d0632f0fb039d53 (diff) | |
| download | bcm5719-llvm-64dae8354b11f1ee8e0f894195d648f659b4b515.tar.gz bcm5719-llvm-64dae8354b11f1ee8e0f894195d648f659b4b515.zip | |
R600/SI: Remove redundant setting expand on f64 vectors
None of these are legal types already, so they default to
Expand.
llvm-svn: 225728
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 41f6d86443e..2c961ff3efd 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -203,13 +203,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : } } - for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) { - MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I); - setOperationAction(ISD::FTRUNC, VT, Expand); - setOperationAction(ISD::FCEIL, VT, Expand); - setOperationAction(ISD::FFLOOR, VT, Expand); - } - if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) { setOperationAction(ISD::FTRUNC, MVT::f64, Legal); setOperationAction(ISD::FCEIL, MVT::f64, Legal); |
