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authorJohnny Chen <johnny.chen@apple.com>2011-03-24 21:36:56 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-03-24 21:36:56 +0000
commit6469ca0c337488c2421368713049c1dc4b26c67b (patch)
tree45c6c2914af2b93a6bb5d8290035f0d6ce82fda6 /llvm/lib/Target
parente0d378b3340c67c774b0e27593347d9c521fe86f (diff)
downloadbcm5719-llvm-6469ca0c337488c2421368713049c1dc4b26c67b.tar.gz
bcm5719-llvm-6469ca0c337488c2421368713049c1dc4b26c67b.zip
T2 Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index b9cafeb831b..f9d2bd0d383 100644
--- a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -1140,7 +1140,7 @@ static bool DisassembleThumb2LdStMul(MCInst &MI, unsigned Opcode, uint32_t insn,
Opcode == ARM::t2STMIA || Opcode == ARM::t2STMIA_UPD ||
Opcode == ARM::t2STMDB || Opcode == ARM::t2STMDB_UPD)
&& "Unexpected opcode");
- assert(NumOps >= 5 && "Thumb2 LdStMul expects NumOps >= 5");
+ assert(NumOps >= 4 && "Thumb2 LdStMul expects NumOps >= 4");
NumOpsAdded = 0;
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