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| author | Bill Wendling <isanbard@gmail.com> | 2010-12-16 00:49:54 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-12-16 00:49:54 +0000 |
| commit | 637813a258bde9c284cc488a0bd0d95b9f4c4b9a (patch) | |
| tree | fce64363015bf877a8f8ee28ccf097ca73a9325e /llvm/lib/Target | |
| parent | c435653998f3db839964d139c7cf950ef6c8cfa6 (diff) | |
| download | bcm5719-llvm-637813a258bde9c284cc488a0bd0d95b9f4c4b9a.tar.gz bcm5719-llvm-637813a258bde9c284cc488a0bd0d95b9f4c4b9a.zip | |
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
llvm-svn: 121931
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp index 4e77bd87cc2..9f917234d13 100644 --- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -356,9 +356,11 @@ static void removeOperands(MachineInstr &MI, unsigned i) { static unsigned convertToNonSPOpcode(unsigned Opcode) { switch (Opcode) { case ARM::tLDRspi: + case ARM::tRestore: // FIXME: Should this opcode be here? return ARM::tLDRi; case ARM::tSTRspi: + case ARM::tSpill: // FIXME: Should this opcode be here? return ARM::tSTRi; } |
