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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-10 00:23:12 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-10 00:23:12 +0000 |
| commit | 618b330dd006b731e07129d4c971eb905707133d (patch) | |
| tree | ff6aa041cbc1bd0c358ebaf31eb0c978cea7504c /llvm/lib/Target | |
| parent | 4593a46cd92ab88e9651ae75f6c623851c353964 (diff) | |
| download | bcm5719-llvm-618b330dd006b731e07129d4c971eb905707133d.tar.gz bcm5719-llvm-618b330dd006b731e07129d4c971eb905707133d.zip | |
AMDGPU: Change vintrp printing to better match sc
Some of the immediates need to be printed differently
eventually.
llvm-svn: 289291
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 21 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 6 |
2 files changed, 15 insertions, 12 deletions
diff --git a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp index 81337f44f01..f95d790e2bc 100644 --- a/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp @@ -679,15 +679,18 @@ void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNum).getImm(); - - if (Imm == 2) { - O << "P0"; - } else if (Imm == 1) { - O << "P20"; - } else if (Imm == 0) { - O << "P10"; - } else { - llvm_unreachable("Invalid interpolation parameter slot"); + switch (Imm) { + case 0: + O << "p10"; + break; + case 1: + O << "p20"; + break; + case 2: + O << "p0"; + break; + default: + O << "invalid_param_" << Imm; } } diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 93e7bcd02a1..9f728110faa 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -52,7 +52,7 @@ multiclass V_INTERP_P1_F32_m : VINTRP_m < 0x00000000, (outs VGPR_32:$vdst), (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr), - "v_interp_p1_f32 $vdst, $i, $attr_chan, $attr, [m0]", + "v_interp_p1_f32 $vdst, $i, $attr_chan, $attr", [(set f32:$vdst, (AMDGPUinterp_p1 f32:$i, (i32 imm:$attr_chan), (i32 imm:$attr)))] >; @@ -75,7 +75,7 @@ defm V_INTERP_P2_F32 : VINTRP_m < 0x00000001, (outs VGPR_32:$vdst), (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), - "v_interp_p2_f32 $vdst, [$src0], $j, $attr_chan, $attr, [m0]", + "v_interp_p2_f32 $vdst, $j, $attr_chan, $attr", [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$j, (i32 imm:$attr_chan), (i32 imm:$attr)))]>; @@ -85,7 +85,7 @@ defm V_INTERP_MOV_F32 : VINTRP_m < 0x00000002, (outs VGPR_32:$vdst), (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr), - "v_interp_mov_f32 $vdst, $src0, $attr_chan, $attr, [m0]", + "v_interp_mov_f32 $vdst, $src0, $attr_chan, $attr", [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan), (i32 imm:$attr)))]>; |
