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| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-05 05:34:08 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-05 05:34:08 +0000 |
| commit | 5fde1b033e67bdc5d2df5f3423ed4c638ece61e6 (patch) | |
| tree | d12dfa8f1a54313e0bec053f32eb1b43d0bbb9c5 /llvm/lib/Target | |
| parent | 1218a40c92caf3b18ddc4dcd797a8514632b12de (diff) | |
| download | bcm5719-llvm-5fde1b033e67bdc5d2df5f3423ed4c638ece61e6.tar.gz bcm5719-llvm-5fde1b033e67bdc5d2df5f3423ed4c638ece61e6.zip | |
Add a SchedMachineModel for the PPC A2
llvm-svn: 178848
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleA2.td | 15 |
2 files changed, 17 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index d6a3ceb18f2..82a69b47695 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -155,7 +155,7 @@ def : ProcessorModel<"e500mc", PPCE500mcModel, def : ProcessorModel<"e5500", PPCE5500Model, [DirectiveE5500, FeatureMFOCRF, Feature64Bit, FeatureSTFIWX, FeatureBookE, FeatureISEL]>; -def : Processor<"a2", PPCA2Itineraries, +def : ProcessorModel<"a2", PPCA2Model, [DirectiveA2, FeatureBookE, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, @@ -163,7 +163,7 @@ def : Processor<"a2", PPCA2Itineraries, FeatureFPRND, FeatureFPCVT, FeatureISEL, FeaturePOPCNTD, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */]>; -def : Processor<"a2q", PPCA2Itineraries, +def : ProcessorModel<"a2q", PPCA2Model, [DirectiveA2, FeatureBookE, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index ba63b5cd8fa..ae084aa0e8c 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -749,3 +749,18 @@ def PPCA2Itineraries : ProcessorItineraries< [15, 7], [FPR_Bypass, FPR_Bypass]> ]>; + +// ===---------------------------------------------------------------------===// +// A2 machine model for scheduling and other instruction cost heuristics. + +def PPCA2Model : SchedMachineModel { + let IssueWidth = 1; // 2 micro-ops are dispatched per cycle. + let MinLatency = -1; // OperandCycles are interpreted as MinLatency. + let LoadLatency = 6; // Optimistic load latency assuming bypass. + // This is overriden by OperandCycles if the + // Itineraries are queried instead. + let MispredictPenalty = 6; + + let Itineraries = PPCA2Itineraries; +} + |
