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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-04-05 10:44:42 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-04-05 10:44:42 +0000 |
| commit | 5fbd93b21a8d22bce222833a1efad5b7bd82bdb1 (patch) | |
| tree | a350d5815c9a237df9ac0faf25e3b2d138a52c6d /llvm/lib/Target | |
| parent | 9d42334e02c25ec77c4f465676806121b56e0764 (diff) | |
| download | bcm5719-llvm-5fbd93b21a8d22bce222833a1efad5b7bd82bdb1.tar.gz bcm5719-llvm-5fbd93b21a8d22bce222833a1efad5b7bd82bdb1.zip | |
[X86][SSE] Renamed combine to make it clear that it only handles the vector shift by immediate opcodes. NFCI
llvm-svn: 299532
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4212635897b..9cbdfac6497 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -31258,9 +31258,9 @@ static SDValue combineShift(SDNode* N, SelectionDAG &DAG, return SDValue(); } -static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const X86Subtarget &Subtarget) { +static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const X86Subtarget &Subtarget) { unsigned Opcode = N->getOpcode(); assert((X86ISD::VSHLI == Opcode || X86ISD::VSRAI == Opcode || X86ISD::VSRLI == Opcode) && @@ -35087,7 +35087,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, case X86ISD::BRCOND: return combineBrCond(N, DAG, Subtarget); case X86ISD::VSHLI: case X86ISD::VSRAI: - case X86ISD::VSRLI: return combineVectorShift(N, DAG, DCI, Subtarget); + case X86ISD::VSRLI: + return combineVectorShiftImm(N, DAG, DCI, Subtarget); case ISD::SIGN_EXTEND_VECTOR_INREG: case ISD::ZERO_EXTEND_VECTOR_INREG: case X86ISD::VSEXT: |
