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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-10-10 10:44:15 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-10-10 10:44:15 +0000
commit5cb3a82892ed66655849b49cd693c69f2139ec5c (patch)
tree50ffbc342b1166f2911b88524a9db4c4df403352 /llvm/lib/Target
parentd227754973a4d4fd8b62798290c79a8be0ea4086 (diff)
downloadbcm5719-llvm-5cb3a82892ed66655849b49cd693c69f2139ec5c.tar.gz
bcm5719-llvm-5cb3a82892ed66655849b49cd693c69f2139ec5c.zip
[TargetLowering] Add root node back to work list after successful SimplifyDemandedBits/SimplifyDemandedVectorElts
Similar to what already happens in the DAGCombiner wrappers, this patch adds the root nodes back onto the worklist if the DCI wrappers' SimplifyDemandedBits/SimplifyDemandedVectorElts were successful. Differential Revision: https://reviews.llvm.org/D53026 llvm-svn: 344132
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp16
1 files changed, 2 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 42c5339f11f..4c18c5a84c2 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36534,16 +36534,10 @@ static SDValue combineMaskedStore(SDNode *N, SelectionDAG &DAG,
// simplify ops leading up to it. We only demand the MSB of each lane.
SDValue Mask = Mst->getMask();
if (Mask.getScalarValueSizeInBits() != 1) {
- TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
- !DCI.isBeforeLegalizeOps());
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedMask(APInt::getSignMask(VT.getScalarSizeInBits()));
- KnownBits Known;
- if (TLI.SimplifyDemandedBits(Mask, DemandedMask, Known, TLO)) {
- DCI.AddToWorklist(Mask.getNode());
- DCI.CommitTargetLoweringOpt(TLO);
+ if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI))
return SDValue(N, 0);
- }
}
// TODO: AVX512 targets should also be able to simplify something like the
@@ -38962,16 +38956,10 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG,
// With AVX2 we only demand the upper bit of the mask.
if (!Subtarget.hasAVX512()) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
- !DCI.isBeforeLegalizeOps());
SDValue Mask = N->getOperand(2);
- KnownBits Known;
APInt DemandedMask(APInt::getSignMask(Mask.getScalarValueSizeInBits()));
- if (TLI.SimplifyDemandedBits(Mask, DemandedMask, Known, TLO)) {
- DCI.AddToWorklist(Mask.getNode());
- DCI.CommitTargetLoweringOpt(TLO);
+ if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI))
return SDValue(N, 0);
- }
}
return SDValue();
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