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| author | Craig Topper <craig.topper@intel.com> | 2019-04-22 06:12:02 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-04-22 06:12:02 +0000 |
| commit | 5c43ab337ff2181e39f4c8ed9504c1da60f69314 (patch) | |
| tree | 4f318d38bd2313ab35bc362dd9591c5cc30da179 /llvm/lib/Target | |
| parent | 7868fb6fdd79927a1f3b2e7185183bf4702f290c (diff) | |
| download | bcm5719-llvm-5c43ab337ff2181e39f4c8ed9504c1da60f69314.tar.gz bcm5719-llvm-5c43ab337ff2181e39f4c8ed9504c1da60f69314.zip | |
[X86] Reject 512-bit types in getRegForInlineAsmConstraint when AVX512 is not enabled. Same for 256 bit and AVX.
llvm-svn: 358872
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 21b412c987a..2534948bb5c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -43676,7 +43676,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // Scalar SSE types. case MVT::f32: case MVT::i32: - if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX()) + if (VConstraint && Subtarget.hasVLX()) return std::make_pair(0U, &X86::FR32XRegClass); return std::make_pair(0U, &X86::FR32RegClass); case MVT::f64: @@ -43704,11 +43704,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case MVT::v4f64: if (VConstraint && Subtarget.hasVLX()) return std::make_pair(0U, &X86::VR256XRegClass); - return std::make_pair(0U, &X86::VR256RegClass); + if (Subtarget.hasAVX()) + return std::make_pair(0U, &X86::VR256RegClass); + break; case MVT::v8f64: case MVT::v16f32: case MVT::v16i32: case MVT::v8i64: + if (!Subtarget.hasAVX512()) break; if (VConstraint) return std::make_pair(0U, &X86::VR512RegClass); return std::make_pair(0U, &X86::VR512_0_15RegClass); |
