diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2018-10-04 14:30:03 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-10-04 14:30:03 +0000 |
| commit | 5bf3b20e9958bb03c68e2a0a739f335ea0086c47 (patch) | |
| tree | 02ea754250f0edc2c3d24a37b101edb9752aa2cd /llvm/lib/Target | |
| parent | 422f7246183b41b9dbe04e93e28edcdaf39e0c22 (diff) | |
| download | bcm5719-llvm-5bf3b20e9958bb03c68e2a0a739f335ea0086c47.tar.gz bcm5719-llvm-5bf3b20e9958bb03c68e2a0a739f335ea0086c47.zip | |
[RISCV] Remove overzealous is64Bit checks
lowerGlobalAddress, lowerBlockAddress, and insertIndirectBranch contain
overzealous checks for is64Bit. These functions are all safe as-implemented
for RV64.
llvm-svn: 343781
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 3 |
2 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9cfd747ffc0..5c347ca4684 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -327,7 +327,7 @@ SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op, int64_t Offset = N->getOffset(); MVT XLenVT = Subtarget.getXLenVT(); - if (isPositionIndependent() || Subtarget.is64Bit()) + if (isPositionIndependent()) report_fatal_error("Unable to lowerGlobalAddress"); // In order to maximise the opportunity for common subexpression elimination, // emit a separate ADD node for the global address offset instead of folding @@ -352,7 +352,7 @@ SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op, const BlockAddress *BA = N->getBlockAddress(); int64_t Offset = N->getOffset(); - if (isPositionIndependent() || Subtarget.is64Bit()) + if (isPositionIndependent()) report_fatal_error("Unable to lowerBlockAddress"); SDValue BAHi = DAG.getTargetBlockAddress(BA, Ty, Offset, RISCVII::MO_HI); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 327e4a7d615..76c74368ca1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -362,9 +362,8 @@ unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, MachineFunction *MF = MBB.getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget()); - const auto &STI = MF->getSubtarget<RISCVSubtarget>(); - if (TM.isPositionIndependent() || STI.is64Bit()) + if (TM.isPositionIndependent()) report_fatal_error("Unable to insert indirect branch"); if (!isInt<32>(BrOffset)) |
