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author | Chad Rosier <mcrosier@apple.com> | 2011-11-04 23:45:39 +0000 |
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committer | Chad Rosier <mcrosier@apple.com> | 2011-11-04 23:45:39 +0000 |
commit | 5b8fdd7b626354b8f1e2383d411e55a715f08cf9 (patch) | |
tree | 612255f1606949f174a94cf53af892dd6031c6cf /llvm/lib/Target | |
parent | 088789caa62ed7b333293a1cd4fc7b053d0069a6 (diff) | |
download | bcm5719-llvm-5b8fdd7b626354b8f1e2383d411e55a715f08cf9.tar.gz bcm5719-llvm-5b8fdd7b626354b8f1e2383d411e55a715f08cf9.zip |
Cannot create a result register for non-legal types.
llvm-svn: 143749
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index a315c305fca..517f73f4e13 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -552,8 +552,9 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { // do so now. const ConstantInt *CI = cast<ConstantInt>(C); if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { + EVT SrcVT = MVT::i32; unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16; - unsigned ImmReg = createResultReg(TLI.getRegClassFor(VT)); + unsigned ImmReg = createResultReg(TLI.getRegClassFor(SrcVT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg) .addImm(CI->getSExtValue())); |