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| author | Hal Finkel <hfinkel@anl.gov> | 2013-11-29 06:32:17 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-11-29 06:32:17 +0000 |
| commit | 5a7162f36b924d68210e8d9e8c881ec483165a58 (patch) | |
| tree | ba91d383cf7821a80f127262fb5f2205fa7b0053 /llvm/lib/Target | |
| parent | 4035e8d86a2fc0e98d5d09f60a61338018117c00 (diff) | |
| download | bcm5719-llvm-5a7162f36b924d68210e8d9e8c881ec483165a58.tar.gz bcm5719-llvm-5a7162f36b924d68210e8d9e8c881ec483165a58.zip | |
Create a PPC440 SchedMachineModel
Some of the older PPC processor definitions don't have associated
SchedMachineModels; correct this for the PPC440.
llvm-svn: 195949
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCSchedule440.td | 14 |
2 files changed, 20 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 54e3d400a9d..18430d47a46 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -153,12 +153,12 @@ include "PPCInstrInfo.td" // def : Processor<"generic", G3Itineraries, [Directive32]>; -def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL, - FeatureFRES, FeatureFRSQRTE, - FeatureBookE, DeprecatedMFTB]>; -def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL, - FeatureFRES, FeatureFRSQRTE, - FeatureBookE, DeprecatedMFTB]>; +def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, + FeatureFRES, FeatureFRSQRTE, + FeatureBookE, DeprecatedMFTB]>; +def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, + FeatureFRES, FeatureFRSQRTE, + FeatureBookE, DeprecatedMFTB]>; def : Processor<"601", G3Itineraries, [Directive601]>; def : Processor<"602", G3Itineraries, [Directive602]>; def : Processor<"603", G3Itineraries, [Directive603, diff --git a/llvm/lib/Target/PowerPC/PPCSchedule440.td b/llvm/lib/Target/PowerPC/PPCSchedule440.td index 11d79f2be01..780fa4779b4 100644 --- a/llvm/lib/Target/PowerPC/PPCSchedule440.td +++ b/llvm/lib/Target/PowerPC/PPCSchedule440.td @@ -555,3 +555,17 @@ def PPC440Itineraries : ProcessorItineraries< [6, 0], [P440_FPR_Bypass, P440_FPR_Bypass]> ]>; + +// ===---------------------------------------------------------------------===// +// PPC440 machine model for scheduling and other instruction cost heuristics. + +def PPC440Model : SchedMachineModel { + let IssueWidth = 2; // 2 instructions are dispatched per cycle. + let MinLatency = -1; // OperandCycles are interpreted as MinLatency. + let LoadLatency = 5; // Optimistic load latency assuming bypass. + // This is overriden by OperandCycles if the + // Itineraries are queried instead. + + let Itineraries = PPC440Itineraries; +} + |
