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| author | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-04-30 16:00:49 +0000 |
|---|---|---|
| committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-04-30 16:00:49 +0000 |
| commit | 56df6ff2c5c291eb67305dc36280b27e3b7f65de (patch) | |
| tree | b513d8eb687b7de61905427938c3a8a2926e9403 /llvm/lib/Target | |
| parent | 8451cdff2ffa2f5473e69b43984f799b1e2533ac (diff) | |
| download | bcm5719-llvm-56df6ff2c5c291eb67305dc36280b27e3b7f65de.tar.gz bcm5719-llvm-56df6ff2c5c291eb67305dc36280b27e3b7f65de.zip | |
[mips] Add instruction alias (dsll and dsrl).
Summary:
The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs.
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D3486
llvm-svn: 207664
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index 7f895e23f99..1303028c689 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -440,6 +440,8 @@ def : InstAlias<"add $rs, $imm", def : InstAlias<"addu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; +def : InstAlias<"dsll $rd, $rt, $rs", + (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>; def : InstAlias<"dsubu $rt, $rs, $imm", (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, InvertedImOperand64: $imm),0>; @@ -449,6 +451,8 @@ def : InstAlias<"dsub $rs, $imm", def : InstAlias<"dsubu $rs, $imm", (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm), 0>; +def : InstAlias<"dsrl $rd, $rt, $rs", + (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>; /// Move between CPU and coprocessor registers let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { |
