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| author | Amara Emerson <aemerson@apple.com> | 2019-08-21 00:12:37 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-08-21 00:12:37 +0000 |
| commit | 56606a4db3e7c6b4a1b3bfd3b2dfc04c81a2247e (patch) | |
| tree | 43e275c99cda9d1e1ef5b20f7565ed8c02569844 /llvm/lib/Target | |
| parent | d979a2993561d42612da5ef45122fb69466967c3 (diff) | |
| download | bcm5719-llvm-56606a4db3e7c6b4a1b3bfd3b2dfc04c81a2247e.tar.gz bcm5719-llvm-56606a4db3e7c6b4a1b3bfd3b2dfc04c81a2247e.zip | |
[AArch64][GlobalISel] Add support for narrowScalar of G_ZEXT
We do this by merging the source with the high bits set to 0.
Differential Revision: https://reviews.llvm.org/D66181
llvm-svn: 369480
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterBankInfo.cpp | 4 |
2 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 3f8bce9b3b9..fcbd2c76f85 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -341,7 +341,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { unsigned DstSize = Query.Types[0].getSizeInBits(); if (DstSize == 128 && !Query.Types[0].isVector()) - return false; // Extending to a scalar s128 is not legal. + return false; // Extending to a scalar s128 needs narrowing. // Make sure that we have something that will fit in a register, and // make sure it's a power of 2. @@ -363,8 +363,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { return true; }; - getActionDefinitionsBuilder({G_ZEXT, G_ANYEXT}).legalIf(ExtLegalFunc); - getActionDefinitionsBuilder(G_SEXT) + getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) .legalIf(ExtLegalFunc) .clampScalar(0, s64, s64); // Just for s128, others are handled above. diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp index 78fede3dcde..daddf423189 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -46,7 +46,9 @@ const RegisterBank &X86RegisterBankInfo::getRegBankFromRegClass( if (X86::GR8RegClass.hasSubClassEq(&RC) || X86::GR16RegClass.hasSubClassEq(&RC) || X86::GR32RegClass.hasSubClassEq(&RC) || - X86::GR64RegClass.hasSubClassEq(&RC)) + X86::GR64RegClass.hasSubClassEq(&RC) || + X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || + X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) return getRegBank(X86::GPRRegBankID); if (X86::FR32XRegClass.hasSubClassEq(&RC) || |
