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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-19 22:19:43 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-03-19 22:19:43 +0000 |
| commit | 547aff20f51d8df72a7005866278055b9f95e34d (patch) | |
| tree | f35b8ffbd8bc18d758aa67a0f73d15031612a1d7 /llvm/lib/Target | |
| parent | 9cd8c38a32f098c811bb205ece892ec687e48f19 (diff) | |
| download | bcm5719-llvm-547aff20f51d8df72a7005866278055b9f95e34d.tar.gz bcm5719-llvm-547aff20f51d8df72a7005866278055b9f95e34d.zip | |
R600/SI: Don't display the GDS bit.
It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.
llvm-svn: 204270
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 57b36b3298a..8973f2898c9 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -395,7 +395,7 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < op, (outs regClass:$vdst), (ins i1imm:$gds, VReg_32:$addr, i16imm:$offset), - asm#" $gds, $vdst, $addr, $offset, [M0]", + asm#" $vdst, $addr, $offset, [M0]", []> { let data0 = 0; let data1 = 0; @@ -407,7 +407,7 @@ class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A < op, (outs), (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset), - asm#" $gds, $addr, $data0, $offset [M0]", + asm#" $addr, $data0, $offset [M0]", []> { let data1 = 0; let mayStore = 1; @@ -419,7 +419,7 @@ class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A < op, (outs rc:$vdst), (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset), - asm#" $gds, $vdst, $addr, $data0, $offset, [M0]", + asm#" $vdst, $addr, $data0, $offset, [M0]", []> { let data1 = 0; |
