diff options
| author | Ana Pazos <apazos@quicinc.com> | 2019-03-08 23:01:08 +0000 |
|---|---|---|
| committer | Ana Pazos <apazos@quicinc.com> | 2019-03-08 23:01:08 +0000 |
| commit | 5254d1baae63dc2db6b991996ce1e8313027da6c (patch) | |
| tree | 5e229d1b981fcf4e350a07d9e0af244cfb4434e8 /llvm/lib/Target | |
| parent | 6e4ec6022f7936b88b42a30f6d64a787609284a9 (diff) | |
| download | bcm5719-llvm-5254d1baae63dc2db6b991996ce1e8313027da6c.tar.gz bcm5719-llvm-5254d1baae63dc2db6b991996ce1e8313027da6c.zip | |
[RISCV] Allow access to FP CSRs without F extension
Summary:
Floating-point CSRs should be accessible even when F extension is not enabled.
But pseudo instructions that access floating point CSRs still require the F extension.
GNU tools already implement this behavior. RISC-V spec is pending update to reflect
this behavior and to extend it to pseudo instructions that access floating point CSRs.
Reviewers: asb
Reviewed By: asb
Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits
Differential Revision: https://reviews.llvm.org/D58932
llvm-svn: 355753
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index c36633d5c63..df8cdcc84dc 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -71,11 +71,9 @@ def : SysReg<"uip", 0x044>; // User Floating-Point CSRs //===-------------------------- -let FeaturesRequired = [{ {RISCV::FeatureStdExtF} }] in { def : SysReg<"fflags", 0x001>; def : SysReg<"frm", 0x002>; def : SysReg<"fcsr", 0x003>; -} //===-------------------------- // User Counter/Timers |
