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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-05-25 16:15:56 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-05-25 16:15:56 +0000 |
| commit | 50828163a15303b96c6ab6e7df30c1d292b4c287 (patch) | |
| tree | 003512294042767181a5ac430f3e003f496cac9e /llvm/lib/Target | |
| parent | ec87f841c64621d03f8ea7536985eef9df80ce06 (diff) | |
| download | bcm5719-llvm-50828163a15303b96c6ab6e7df30c1d292b4c287.tar.gz bcm5719-llvm-50828163a15303b96c6ab6e7df30c1d292b4c287.zip | |
R600/SI: Remove some unnecessary patterns from VINTRP multiclass
DisableEncoding and Constraints can be set using let statements around
the multiclass defs.
llvm-svn: 238148
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 8 |
2 files changed, 9 insertions, 11 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 12e9d4f24bb..587ddb5cd1a 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -1771,16 +1771,12 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins, SIMCInstr<opName, SISubtarget.VI>; multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm, - list<dag> pattern = [], - string disableEncoding = "", string constraints = ""> { - let DisableEncoding = disableEncoding, - Constraints = constraints in { - def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>; + list<dag> pattern = []> { + def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>; - def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>; + def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>; - def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>; - } + def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 15c2f3ec193..d92c4b62398 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1461,15 +1461,17 @@ defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m; } // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst" +let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in { + defm V_INTERP_P2_F32 : VINTRP_m < 0x00000001, (outs VGPR_32:$dst), (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]", [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan), - (i32 imm:$attr)))], - "$src0", - "$src0 = $dst">; + (i32 imm:$attr)))]>; + +} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst" defm V_INTERP_MOV_F32 : VINTRP_m < 0x00000002, |
