diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-02 00:02:45 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-06-02 00:02:45 +0000 |
| commit | 4e76bf82829970b2fbe6efdb6209c1af72544a37 (patch) | |
| tree | e1d3e64b603c1e3faf5391826ef1cae960ce9b7c /llvm/lib/Target | |
| parent | 56bf023a6db4ee542e568e0568933dcca670483e (diff) | |
| download | bcm5719-llvm-4e76bf82829970b2fbe6efdb6209c1af72544a37.tar.gz bcm5719-llvm-4e76bf82829970b2fbe6efdb6209c1af72544a37.zip | |
Expand unaligned i16 loads/stores for the Mips backend.
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.
llvm-svn: 157862
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 6ea2692d6f8..d0ea2185e0c 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -292,7 +292,6 @@ bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { switch (SVT) { case MVT::i64: case MVT::i32: - case MVT::i16: return true; case MVT::f32: return Subtarget->hasMips32r2Or64(); |
