summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorEric Christopher <echristo@gmail.com>2015-03-21 04:22:23 +0000
committerEric Christopher <echristo@gmail.com>2015-03-21 04:22:23 +0000
commit4d0f35a901efd6f02d7583b08b7741b217be15e5 (patch)
treeabfae00418b65855bf2e16d7a460b3e7baef681f /llvm/lib/Target
parentfaad6205696fa07ef9a51bfc1f8e667a6d9005cd (diff)
downloadbcm5719-llvm-4d0f35a901efd6f02d7583b08b7741b217be15e5.tar.gz
bcm5719-llvm-4d0f35a901efd6f02d7583b08b7741b217be15e5.zip
Remove the target independent TargetMachine::getSubtarget and
TargetMachine::getSubtargetImpl routines. This keeps the target independent code free of bare subtarget calls while the remainder of the backends are migrated, or not if they don't wish to support per-function subtargets as would be needed for function multiversioning or LTO of disparate cpu subarchitecture types, e.g. clang -msse4.2 -c foo.c -emit-llvm -o foo.bc clang -c bar.c -emit-llvm -o bar.bc llvm-link foo.bc bar.bc -o baz.bc llc baz.bc and get appropriate code for what the command lines requested. llvm-svn: 232885
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.h2
-rw-r--r--llvm/lib/Target/BPF/BPFTargetMachine.h5
-rw-r--r--llvm/lib/Target/CppBackend/CPPTargetMachine.h9
-rw-r--r--llvm/lib/Target/Hexagon/HexagonTargetMachine.h2
-rw-r--r--llvm/lib/Target/MSP430/MSP430TargetMachine.h2
-rw-r--r--llvm/lib/Target/Mips/MipsTargetMachine.h2
-rw-r--r--llvm/lib/Target/NVPTX/NVPTXTargetMachine.h5
-rw-r--r--llvm/lib/Target/R600/AMDGPUTargetMachine.h3
-rw-r--r--llvm/lib/Target/Sparc/SparcTargetMachine.h4
-rw-r--r--llvm/lib/Target/SystemZ/SystemZTargetMachine.h3
-rw-r--r--llvm/lib/Target/XCore/XCoreTargetMachine.h5
11 files changed, 24 insertions, 18 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index e7f67da5f96..20ca97b616b 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -44,7 +44,7 @@ public:
bool isLittle);
~ARMBaseTargetMachine() override;
- const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
bool isLittleEndian() const { return isLittle; }
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.h b/llvm/lib/Target/BPF/BPFTargetMachine.h
index 1bfaafc6a58..6aeafb99a2a 100644
--- a/llvm/lib/Target/BPF/BPFTargetMachine.h
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.h
@@ -27,7 +27,10 @@ public:
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);
- const BPFSubtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }
+ const BPFSubtarget *getSubtargetImpl(const Function &) const override {
+ return &Subtarget;
+ }
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/CppBackend/CPPTargetMachine.h b/llvm/lib/Target/CppBackend/CPPTargetMachine.h
index 96d832df170..678a932cb28 100644
--- a/llvm/lib/Target/CppBackend/CPPTargetMachine.h
+++ b/llvm/lib/Target/CppBackend/CPPTargetMachine.h
@@ -22,20 +22,13 @@ namespace llvm {
class formatted_raw_ostream;
-class CPPSubtarget : public TargetSubtargetInfo {
-};
-
struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL)
- : TargetMachine(T, "", TT, CPU, FS, Options), Subtarget() {}
-
-private:
- CPPSubtarget Subtarget;
+ : TargetMachine(T, "", TT, CPU, FS, Options) {}
public:
- const CPPSubtarget *getSubtargetImpl() const override { return &Subtarget; }
bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out,
CodeGenFileType FileType, bool DisableVerify,
AnalysisID StartAfter,
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index cae49e9d8cf..5774f7e195b 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -32,7 +32,7 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
~HexagonTargetMachine() override;
- const HexagonSubtarget *getSubtargetImpl() const override {
+ const HexagonSubtarget *getSubtargetImpl(const Function &) const override {
return &Subtarget;
}
static unsigned getModuleMatchQuality(const Module &M);
diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/llvm/lib/Target/MSP430/MSP430TargetMachine.h
index 0e54ed631be..6ccd30d393f 100644
--- a/llvm/lib/Target/MSP430/MSP430TargetMachine.h
+++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.h
@@ -34,7 +34,7 @@ public:
CodeGenOpt::Level OL);
~MSP430TargetMachine() override;
- const MSP430Subtarget *getSubtargetImpl() const override {
+ const MSP430Subtarget *getSubtargetImpl(const Function &F) const override {
return &Subtarget;
}
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index ebaf5e0aefe..5427d6a8304 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -46,7 +46,7 @@ public:
TargetIRAnalysis getTargetIRAnalysis() override;
- const MipsSubtarget *getSubtargetImpl() const override {
+ const MipsSubtarget *getSubtargetImpl() const {
if (Subtarget)
return Subtarget;
return &DefaultSubtarget;
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
index 8636d8a36f0..b8df5affe5b 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
@@ -39,7 +39,10 @@ public:
CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
~NVPTXTargetMachine() override;
- const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const NVPTXSubtarget *getSubtargetImpl(const Function &) const override {
+ return &Subtarget;
+ }
+ const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
bool is64Bit() const { return is64bit; }
NVPTX::DrvInterface getDrvInterface() const { return drvInterface; }
ManagedStringPool *getManagedStrPool() const {
diff --git a/llvm/lib/Target/R600/AMDGPUTargetMachine.h b/llvm/lib/Target/R600/AMDGPUTargetMachine.h
index 8fc66b1fcd2..785c119a102 100644
--- a/llvm/lib/Target/R600/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/R600/AMDGPUTargetMachine.h
@@ -42,7 +42,8 @@ public:
CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine();
- const AMDGPUSubtarget *getSubtargetImpl() const override {
+ const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
+ const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override {
return &Subtarget;
}
const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 096e7c8485a..30a8ebf75d9 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -30,7 +30,9 @@ public:
CodeGenOpt::Level OL, bool is64bit);
~SparcTargetMachine() override;
- const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const SparcSubtarget *getSubtargetImpl(const Function &) const override {
+ return &Subtarget;
+ }
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
index 7d8dce77a63..181b92640e7 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -33,7 +33,8 @@ public:
CodeGenOpt::Level OL);
~SystemZTargetMachine() override;
- const SystemZSubtarget *getSubtargetImpl() const override {
+ const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }
+ const SystemZSubtarget *getSubtargetImpl(const Function &) const override {
return &Subtarget;
}
// Override LLVMTargetMachine
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.h b/llvm/lib/Target/XCore/XCoreTargetMachine.h
index 03b73cd6987..0d324ab1e72 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.h
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.h
@@ -29,7 +29,10 @@ public:
CodeGenOpt::Level OL);
~XCoreTargetMachine() override;
- const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
+ const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }
+ const XCoreSubtarget *getSubtargetImpl(const Function &) const override {
+ return &Subtarget;
+ }
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
OpenPOWER on IntegriCloud