Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API."

This reverts commit r301105, 4, 3 and 1, as a follow up of the previous
revert, which broke even more bots.

For reference:
Revert "[APInt] Use operator<<= where possible. NFC"
Revert "[APInt] Use operator<<= instead of shl where possible. NFC"
Revert "[APInt] Use ashInPlace where possible."

PR32754.

llvm-svn: 301111

3 files changed, 17 insertions, 16 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 309714570b5..7141e77fcd2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1852,17 +1852,17 @@ static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
   OpUsefulBits = 1;
 
   if (MSB >= Imm) {
-    OpUsefulBits <<= MSB - Imm + 1;
+    OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
     --OpUsefulBits;
     // The interesting part will be in the lower part of the result
     getUsefulBits(Op, OpUsefulBits, Depth + 1);
     // The interesting part was starting at Imm in the argument
-    OpUsefulBits <<= Imm;
+    OpUsefulBits = OpUsefulBits.shl(Imm);
   } else {
-    OpUsefulBits <<= MSB + 1;
+    OpUsefulBits = OpUsefulBits.shl(MSB + 1);
     --OpUsefulBits;
     // The interesting part will be shifted in the result
-    OpUsefulBits <<= OpUsefulBits.getBitWidth() - Imm;
+    OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
     getUsefulBits(Op, OpUsefulBits, Depth + 1);
     // The interesting part was at zero in the argument
     OpUsefulBits.lshrInPlace(OpUsefulBits.getBitWidth() - Imm);
@@ -1892,7 +1892,7 @@ static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
   if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
     // Shift Left
     uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
-    Mask <<= ShiftAmt;
+    Mask = Mask.shl(ShiftAmt);
     getUsefulBits(Op, Mask, Depth + 1);
     Mask.lshrInPlace(ShiftAmt);
   } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
@@ -1902,7 +1902,7 @@ static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
     uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
     Mask.lshrInPlace(ShiftAmt);
     getUsefulBits(Op, Mask, Depth + 1);
-    Mask <<= ShiftAmt;
+    Mask = Mask.shl(ShiftAmt);
   } else
     return;
 
@@ -1930,13 +1930,13 @@ static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
     uint64_t Width = MSB - Imm + 1;
     uint64_t LSB = Imm;
 
-    OpUsefulBits <<= Width;
+    OpUsefulBits = OpUsefulBits.shl(Width);
     --OpUsefulBits;
 
     if (Op.getOperand(1) == Orig) {
       // Copy the low bits from the result to bits starting from LSB.
       Mask = ResultUsefulBits & OpUsefulBits;
-      Mask <<= LSB;
+      Mask = Mask.shl(LSB);
     }
 
     if (Op.getOperand(0) == Orig)
@@ -1947,9 +1947,9 @@ static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
     uint64_t Width = MSB + 1;
     uint64_t LSB = UsefulBits.getBitWidth() - Imm;
 
-    OpUsefulBits <<= Width;
+    OpUsefulBits = OpUsefulBits.shl(Width);
     --OpUsefulBits;
-    OpUsefulBits <<= LSB;
+    OpUsefulBits = OpUsefulBits.shl(LSB);
 
     if (Op.getOperand(1) == Orig) {
       // Copy the bits from the result to the zero bits.
diff --git a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
index 39f43988b19..7189b5a52c4 100644
--- a/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
@@ -124,7 +124,7 @@ void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
       // FP immediates are used only when setting GPRs, so they may be dealt
       // with like regular immediates from this point on.
       auto Expr = HexagonMCExpr::create(
-          MCConstantExpr::create(Val.bitcastToAPInt().getZExtValue(),
+          MCConstantExpr::create(*Val.bitcastToAPInt().getRawData(),
                                  AP.OutContext),
           AP.OutContext);
       HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d5bc4436f8e..e3de30417b0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -26717,8 +26717,8 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
       DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
       unsigned ShAmt = ShiftImm->getZExtValue();
       if (Opc == X86ISD::VSHLI) {
-        KnownZero <<= ShAmt;
-        KnownOne <<= ShAmt;
+        KnownZero = KnownZero << ShAmt;
+        KnownOne = KnownOne << ShAmt;
         // Low bits are known zero.
         KnownZero.setLowBits(ShAmt);
       } else {
@@ -31054,7 +31054,8 @@ static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG) {
       N0.getOperand(1).getOpcode() == ISD::Constant) {
     SDValue N00 = N0.getOperand(0);
     APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
-    Mask <<= N1C->getAPIntValue();
+    const APInt &ShAmt = N1C->getAPIntValue();
+    Mask = Mask.shl(ShAmt);
     bool MaskOK = false;
     // We can handle cases concerning bit-widening nodes containing setcc_c if
     // we carefully interrogate the mask to make sure we are semantics
@@ -31264,9 +31265,9 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
     unsigned ShiftImm = ShiftVal.getZExtValue();
     for (APInt &Elt : EltBits) {
       if (X86ISD::VSHLI == Opcode)
-        Elt <<= ShiftImm;
+        Elt = Elt.shl(ShiftImm);
       else if (X86ISD::VSRAI == Opcode)
-        Elt.ashrInPlace(ShiftImm);
+        Elt = Elt.ashr(ShiftImm);
       else
         Elt.lshrInPlace(ShiftImm);
     }