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| author | Andrew V. Tischenko <andrew.v.tischenko@gmail.com> | 2017-12-07 11:19:49 +0000 |
|---|---|---|
| committer | Andrew V. Tischenko <andrew.v.tischenko@gmail.com> | 2017-12-07 11:19:49 +0000 |
| commit | 44cfc51415e6acc6ea53029d7499923864a4cd5d (patch) | |
| tree | 53b4052a9846c168518191849dec07be252cbde2 /llvm/lib/Target | |
| parent | e385d0096021f0674c510fea7fef143d15785702 (diff) | |
| download | bcm5719-llvm-44cfc51415e6acc6ea53029d7499923864a4cd5d.tar.gz bcm5719-llvm-44cfc51415e6acc6ea53029d7499923864a4cd5d.zip | |
Add proper BTVER2 sched support for MOV instr.
Differential Revision: https://reviews.llvm.org/D40345
llvm-svn: 320034
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index a2f02962444..685aaf1f140 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -166,7 +166,7 @@ def: InstRW<[WriteSHLDm], (instregex "SHRD(16|32|64)mr(i8|CL)")>; def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; } def : WriteRes<WriteStore, [JSAGU]>; -def : WriteRes<WriteMove, [JAny]>; +def : WriteRes<WriteMove, [JALU01]>; //////////////////////////////////////////////////////////////////////////////// // Idioms that clear a register, like xorps %xmm0, %xmm0. |
