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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-04 16:34:39 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-04-04 16:34:39 +0000 |
| commit | 3e90f84806e40b0818c3003b24e558bef63db18b (patch) | |
| tree | 6c67fb574b6d0b470df75a43a1cac02037c26c71 /llvm/lib/Target | |
| parent | 236da200f10ff1f416d93994ea010ff57db56a82 (diff) | |
| download | bcm5719-llvm-3e90f84806e40b0818c3003b24e558bef63db18b.tar.gz bcm5719-llvm-3e90f84806e40b0818c3003b24e558bef63db18b.zip | |
AMDGPU: Remove legacy export intrinsic
llvm-svn: 299444
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 23 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIIntrinsics.td | 13 |
2 files changed, 0 insertions, 36 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 089d31e818e..36f16e3ca9a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3159,29 +3159,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Src); return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, Cast); } - case AMDGPUIntrinsic::SI_export: { // Legacy intrinsic. - const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(2)); - const ConstantSDNode *VM = cast<ConstantSDNode>(Op.getOperand(3)); - const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(4)); - const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(5)); - const ConstantSDNode *Compr = cast<ConstantSDNode>(Op.getOperand(6)); - - const SDValue Ops[] = { - Chain, - DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), - DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8), - Op.getOperand(7), // src0 - Op.getOperand(8), // src1 - Op.getOperand(9), // src2 - Op.getOperand(10), // src3 - DAG.getTargetConstant(Compr->getZExtValue(), DL, MVT::i1), - DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1) - }; - - unsigned Opc = Done->isNullValue() ? - AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE; - return DAG.getNode(Opc, DL, Op->getVTList(), Ops); - } default: return Op; } diff --git a/llvm/lib/Target/AMDGPU/SIIntrinsics.td b/llvm/lib/Target/AMDGPU/SIIntrinsics.td index 1fab017f99b..7b7cf163505 100644 --- a/llvm/lib/Target/AMDGPU/SIIntrinsics.td +++ b/llvm/lib/Target/AMDGPU/SIIntrinsics.td @@ -14,19 +14,6 @@ let TargetPrefix = "SI", isTarget = 1 in { - def int_SI_export : Intrinsic <[], - [llvm_i32_ty, // en - llvm_i32_ty, // vm (FIXME: should be i1) - llvm_i32_ty, // done (FIXME: should be i1) - llvm_i32_ty, // tgt - llvm_i32_ty, // compr (FIXME: should be i1) - llvm_float_ty, // src0 - llvm_float_ty, // src1 - llvm_float_ty, // src2 - llvm_float_ty], // src3 - [] - >; - def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed |
