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authorNirav Dave <niravd@google.com>2017-12-01 21:55:47 +0000
committerNirav Dave <niravd@google.com>2017-12-01 21:55:47 +0000
commit3e76e1e89e27d8015746a155301d57b0e3047849 (patch)
tree8f452f17cc94fade3417c9473f23cff07a797da0 /llvm/lib/Target
parent3da7982cca9dde69213d2f47adc7981b6072ee31 (diff)
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[DAG][ARM] Revert "Reenable post-legalize store merge"
due to failures in AArch and ARM code gen. llvm-svn: 319587
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index a791e2ea233..01f101d5bd5 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -532,6 +532,9 @@ class VectorType;
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
unsigned &Cost) const override;
+ // Disable currently because of invalid merge.
+ bool mergeStoresAfterLegalization() const override { return false; }
+
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
const SelectionDAG &DAG) const override {
// Do not merge to larger than i32.
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