summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorJim Grosbach <grosbach@apple.com>2008-10-01 18:16:49 +0000
committerJim Grosbach <grosbach@apple.com>2008-10-01 18:16:49 +0000
commit3dc0a3bce3b29d7fa8b03e05669f9dedc2f0342c (patch)
tree06922bfdd6f2f8e2fbfcf55693172b81e42cdd16 /llvm/lib/Target
parentd65a4daeead235fbe3a66b9afcf8044df7f53bff (diff)
downloadbcm5719-llvm-3dc0a3bce3b29d7fa8b03e05669f9dedc2f0342c.tar.gz
bcm5719-llvm-3dc0a3bce3b29d7fa8b03e05669f9dedc2f0342c.zip
Fix typo s/ther/there/
llvm-svn: 56924
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARMCodeEmitter.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
index 4727281d943..ceb6fc57cac 100644
--- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -390,7 +390,7 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
++OpIdx;
}
- // Encode first non-shifter register operand if ther is one.
+ // Encode first non-shifter register operand if there is one.
unsigned Format = TID.TSFlags & ARMII::FormMask;
bool isUnary = (Format == ARMII::DPRdMisc ||
Format == ARMII::DPRdIm ||
OpenPOWER on IntegriCloud