diff options
| author | Duncan Sands <baldrick@free.fr> | 2008-12-01 11:41:29 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-12-01 11:41:29 +0000 |
| commit | 3d960941b1feecb94c19c232ad992b32ac1bc864 (patch) | |
| tree | 83c375467df8179cdf824102583d54a6b750f29c /llvm/lib/Target | |
| parent | 6ed40141f7e3ea38589b67fd15ac48b93c1c8fa1 (diff) | |
| download | bcm5719-llvm-3d960941b1feecb94c19c232ad992b32ac1bc864.tar.gz bcm5719-llvm-3d960941b1feecb94c19c232ad992b32ac1bc864.zip | |
There are no longer any places that require a
MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.
llvm-svn: 60349
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
7 files changed, 21 insertions, 21 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 1f6294f03c3..69452c13601 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1021,8 +1021,8 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { ArgValues.push_back(Root); // Return the new list of results. - return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], - ArgValues.size()); + return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + &ArgValues[0], ArgValues.size()); } /// isFloatingPointZero - Return true if this is +0.0. diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index 66d66d0d8aa..7b0fcca9a37 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -294,8 +294,8 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, ArgValues.push_back(Root); // Return the new list of results. - return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], - ArgValues.size()); + return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + &ArgValues[0], ArgValues.size()); } static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index bca8a4104f8..184f0b23fa5 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1047,8 +1047,8 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex) ArgValues.push_back(Root); // Return the new list of results. - return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], - ArgValues.size()); + return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + &ArgValues[0], ArgValues.size()); } /// isLSAAddress - Return the immediate to use if the specified diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 60f96ae4dd3..bc0294f4a02 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -778,8 +778,8 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], - ResultVals.size()).getNode(); + return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + &ResultVals[0], ResultVals.size()).getNode(); } //===----------------------------------------------------------------------===// @@ -921,8 +921,8 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) ArgValues.push_back(Root); // Return the new list of results. - return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], - ArgValues.size()).getValue(Op.getResNo()); + return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d72fdf6ee50..58fd67505f7 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1261,7 +1261,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { SDValue Ops[] = { CallResult.first, CallResult.second }; - return DAG.getMergeValues(Ops, 2, false); + return DAG.getMergeValues(Ops, 2); } SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, @@ -1825,8 +1825,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, ArgValues.push_back(Root); // Return the new list of results. - return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], - ArgValues.size()); + return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + &ArgValues[0], ArgValues.size()); } /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus @@ -2605,8 +2605,8 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG, // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - SDValue Res = DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], - ResultVals.size()); + SDValue Res = DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), + &ResultVals[0], ResultVals.size()); return Res.getValue(Op.getResNo()); } diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 59e19d54666..7b7bf096847 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -449,8 +449,8 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) { ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], - ResultVals.size()); + return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0], + ResultVals.size()); } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0540538a9d3..109609b4369 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1048,8 +1048,8 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, // Merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], - ResultVals.size()).getNode(); + return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0], + ResultVals.size()).getNode(); } @@ -1431,8 +1431,8 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); // Return the new list of results. - return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], - ArgValues.size()).getValue(Op.getResNo()); + return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), + &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); } SDValue |

