Enhance APFloat to retain bits of NaNs (fixes oggenc).

Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632

6 files changed, 16 insertions, 16 deletions

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index a274c14eabf..d6ca1481395 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1033,14 +1033,14 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
 /// isFloatingPointZero - Return true if this is +0.0.
 static bool isFloatingPointZero(SDOperand Op) {
   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
-    return CFP->isExactlyValue(0.0);
+    return CFP->getValueAPF().isPosZero();
   else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
     // Maybe this has already been legalized into the constant pool?
     if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
       SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
       if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
         if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
-          return CFP->isExactlyValue(0.0);
+          return CFP->getValueAPF().isPosZero();
     }
   }
   return false;
diff --git a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 4f7533cd98e..df976fd31e8 100644
--- a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -131,15 +131,15 @@ namespace {
 
     static bool isFPZ(SDOperand N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
-      return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
+      return (CN && (CN->getValueAPF().isZero()));
     }
     static bool isFPZn(SDOperand N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
-      return (CN && CN->isExactlyValue(-0.0));
+      return (CN && CN->getValueAPF().isNegZero());
     }
     static bool isFPZp(SDOperand N) {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
-      return (CN && CN->isExactlyValue(+0.0));
+      return (CN && CN->getValueAPF().isPosZero());
     }
 
   public:
@@ -334,11 +334,11 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
     bool isDouble = N->getValueType(0) == MVT::f64;
     MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
-    if (CN->isExactlyValue(+0.0)) {
+    if (CN->getValueAPF().isPosZero()) {
       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
                                   T, CurDAG->getRegister(Alpha::F31, T),
                                   CurDAG->getRegister(Alpha::F31, T));
-    } else if ( CN->isExactlyValue(-0.0)) {
+    } else if (CN->getValueAPF().isNegZero()) {
       return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
                                   T, CurDAG->getRegister(Alpha::F31, T),
                                   CurDAG->getRegister(Alpha::F31, T));
diff --git a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 53b704eb9ef..7421978dae9 100644
--- a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -404,9 +404,9 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
     SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
 
     SDOperand V;
-    if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
+    if (cast<ConstantFPSDNode>(N)->getValueAPF().isPosZero()) {
       V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
-    } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
+    } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(APFloat(+1.0))) {
       V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
     } else
       assert(0 && "Unexpected FP constant!");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f2de2a30382..0528eaf80a3 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -362,12 +362,12 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
 static bool isFloatingPointZero(SDOperand Op) {
   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
-    return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
+    return CFP->getValueAPF().isZero();
   else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
     // Maybe this has already been legalized into the constant pool?
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
       if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
-        return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
+        return CFP->getValueAPF().isZero();
   }
   return false;
 }
@@ -530,7 +530,7 @@ bool PPC::isAllNegativeZeroVector(SDNode *N) {
   assert(N->getOpcode() == ISD::BUILD_VECTOR);
   if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
     if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
-      return CFP->isExactlyValue(-0.0);
+      return CFP->getValueAPF().isNegZero();
   return false;
 }
 
@@ -622,7 +622,7 @@ SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
     ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
   } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
     assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
-    Value = FloatToBits(CN->getValue());
+    Value = FloatToBits(CN->getValueAPF().convertToFloat());
     ValSizeInBytes = 4;
   }
 
@@ -2194,7 +2194,7 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
     } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
       assert(CN->getValueType(0) == MVT::f32 &&
              "Only one legal FP vector type!");
-      EltBits = FloatToBits(CN->getValue());
+      EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
     } else {
       // Nonconstant element.
       return true;
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 812d2ecbd2d..81a4838e2d7 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -817,7 +817,7 @@ static inline bool isZeroNode(SDOperand Elt) {
   return ((isa<ConstantSDNode>(Elt) &&
   cast<ConstantSDNode>(Elt)->getValue() == 0) ||
   (isa<ConstantFPSDNode>(Elt) &&
-  cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
+  cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
 }
 
 
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 99fc9bae638..85c9691e5e0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2303,7 +2303,7 @@ static inline bool isZeroNode(SDOperand Elt) {
   return ((isa<ConstantSDNode>(Elt) &&
            cast<ConstantSDNode>(Elt)->getValue() == 0) ||
           (isa<ConstantFPSDNode>(Elt) &&
-           cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
+           cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
 }
 
 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved