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| author | Eli Friedman <eli.friedman@gmail.com> | 2011-12-28 21:24:44 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2011-12-28 21:24:44 +0000 |
| commit | 3a01ddb7e94a724b32f425a5f549ad9b544a35ea (patch) | |
| tree | 0a04900278c66d77f142b4c8ab49226e81dd1c71 /llvm/lib/Target | |
| parent | 5bdf7dcb2d2216932abcfe4392de29783efd2a68 (diff) | |
| download | bcm5719-llvm-3a01ddb7e94a724b32f425a5f549ad9b544a35ea.tar.gz bcm5719-llvm-3a01ddb7e94a724b32f425a5f549ad9b544a35ea.zip | |
Fix type-checking for load transformation which is not legal on floating-point types. PR11674.
llvm-svn: 147323
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 00b46d2cf67..28cd252ce81 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -13924,7 +13924,8 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, // shuffle. We need SSE4 for the shuffles. // TODO: It is possible to support ZExt by zeroing the undef values // during the shuffle phase or after the shuffle. - if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { + if (RegVT.isVector() && RegVT.isInteger() && + Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { assert(MemVT != RegVT && "Cannot extend to the same type"); assert(MemVT.isVector() && "Must load a vector from memory"); |
