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| author | Chris Lattner <sabre@nondot.org> | 2005-07-10 00:29:18 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-07-10 00:29:18 +0000 |
| commit | 36db1ed06fe3fc2013af90e29e66d863cf783892 (patch) | |
| tree | 0cf6f34a0f84fba77b48600f72907298ed7eaf1b /llvm/lib/Target | |
| parent | 9bfa5495dd5458f0ff233ac731999c68885d15f0 (diff) | |
| download | bcm5719-llvm-36db1ed06fe3fc2013af90e29e66d863cf783892.tar.gz bcm5719-llvm-36db1ed06fe3fc2013af90e29e66d863cf783892.zip | |
Change TRUNCSTORE to use a VTSDNode operand instead of being an MVTSTDNode
llvm-svn: 22366
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelPattern.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelPattern.cpp | 9 |
6 files changed, 14 insertions, 13 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index 32259631ce1..aeb15a02f50 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -419,7 +419,7 @@ SDOperand AlphaTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, DAG.getConstant(8, MVT::i64)); return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1, DAG.getConstant(VarArgsOffset, MVT::i64), SA2, - DAG.getSrcValue(VAListV, 8), MVT::i32); + DAG.getSrcValue(VAListV, 8), DAG.getValueType(MVT::i32)); } std::pair<SDOperand,SDOperand> AlphaTargetLowering:: @@ -457,7 +457,8 @@ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, DAG.getConstant(8, MVT::i64)); SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Result.getValue(1), NewOffset, - Tmp, DAG.getSrcValue(VAListV, 8), MVT::i32); + Tmp, DAG.getSrcValue(VAListV, 8), + DAG.getValueType(MVT::i32)); Result = DAG.getNode(ISD::TRUNCATE, getValueType(ArgTy), Result); return std::make_pair(Result, Update); @@ -478,7 +479,8 @@ LowerVACopy(SDOperand Chain, SDOperand SrcP, Value *SrcV, SDOperand DestP, SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP, DAG.getConstant(8, MVT::i64)); return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1), - Val, NPD, DAG.getSrcValue(DestV, 8), MVT::i32); + Val, NPD, DAG.getSrcValue(DestV, 8), + DAG.getValueType(MVT::i32)); } namespace { @@ -2283,7 +2285,7 @@ void AlphaISel::Select(SDOperand N) { case MVT::f32: Opc = Alpha::STS; break; } } else { //ISD::TRUNCSTORE - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { + switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) { default: assert(0 && "unknown Type in store"); case MVT::i1: //FIXME: DAG does not promote this load case MVT::i8: Opc = Alpha::STB; break; diff --git a/llvm/lib/Target/IA64/IA64ISelPattern.cpp b/llvm/lib/Target/IA64/IA64ISelPattern.cpp index a93e2ead274..3b3f90a489c 100644 --- a/llvm/lib/Target/IA64/IA64ISelPattern.cpp +++ b/llvm/lib/Target/IA64/IA64ISelPattern.cpp @@ -2361,7 +2361,7 @@ void ISel::Select(SDOperand N) { case MVT::f64: Opc = IA64::STF8; break; } } else { // truncstore - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { + switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) { default: assert(0 && "unknown type in truncstore"); case MVT::i1: Opc = IA64::ST1; isBool=true; break; //FIXME: DAG does not promote this load? diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index b29b11f182b..f5a09a7f60f 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -2530,7 +2530,7 @@ void ISel::Select(SDOperand N) { case MVT::f32: Opc = PPC::STFS; break; } } else { //ISD::TRUNCSTORE - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { + switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) { default: assert(0 && "unknown Type in store"); case MVT::i1: case MVT::i8: Opc = PPC::STB; break; diff --git a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp index 6761ab1115c..1fca3391707 100644 --- a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp @@ -1593,7 +1593,7 @@ void ISel::Select(SDOperand N) { case MVT::f32: Opc = PPC::STFS; break; } } else { //ISD::TRUNCSTORE - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { + switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) { default: assert(0 && "unknown Type in store"); case MVT::i1: //FIXME: DAG does not promote this load case MVT::i8: Opc= PPC::STB; break; diff --git a/llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp b/llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp index e19e14c12b3..c2740e339be 100644 --- a/llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp +++ b/llvm/lib/Target/SparcV8/SparcV8ISelPattern.cpp @@ -489,7 +489,7 @@ void ISel::Select(SDOperand N) { Tmp2 = SelectExpr(Address); unsigned VT = opcode == ISD::STORE ? - Value.getValueType() : cast<MVTSDNode>(Node)->getExtraValueType(); + Value.getValueType() : cast<VTSDNode>(Node->getOperand(4))->getVT(); switch(VT) { default: assert(0 && "unknown Type in store"); case MVT::f64: Opc = V8::STDFrr; break; diff --git a/llvm/lib/Target/X86/X86ISelPattern.cpp b/llvm/lib/Target/X86/X86ISelPattern.cpp index d7a1c4d01d8..af75bdc7796 100644 --- a/llvm/lib/Target/X86/X86ISelPattern.cpp +++ b/llvm/lib/Target/X86/X86ISelPattern.cpp @@ -4009,7 +4009,7 @@ static SDOperand GetAdjustedArgumentStores(SDOperand Chain, int Offset, StoreVT = Chain.getOperand(1).getValueType(); break; case ISD::TRUNCSTORE: // FLOAT store - StoreVT = cast<MVTSDNode>(Chain)->getExtraValueType(); + StoreVT = cast<VTSDNode>(Chain.getOperand(4))->getVT(); break; } @@ -4043,7 +4043,7 @@ static SDOperand GetAdjustedArgumentStores(SDOperand Chain, int Offset, FIN); assert(Chain.getOpcode() == ISD::TRUNCSTORE); return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, InChain, Chain.getOperand(1), - FIN, DAG.getSrcValue(NULL), StoreVT); + FIN, DAG.getSrcValue(NULL), DAG.getValueType(StoreVT)); } @@ -4366,10 +4366,9 @@ void ISel::Select(SDOperand N) { SelectExpr(N.getValue(0)); return; - case ISD::TRUNCSTORE: { // truncstore chain, val, ptr :storety - // On X86, we can represent all types except for Bool and Float natively. + case ISD::TRUNCSTORE: { // truncstore chain, val, ptr, SRCVALUE, storety X86AddressMode AM; - MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType(); + MVT::ValueType StoredTy = cast<VTSDNode>(N.getOperand(4))->getVT(); assert((StoredTy == MVT::i1 || StoredTy == MVT::f32 || StoredTy == MVT::i16 /*FIXME: THIS IS JUST FOR TESTING!*/) && "Unsupported TRUNCSTORE for this target!"); |

