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authorDiana Picus <diana.picus@linaro.org>2016-12-19 14:07:50 +0000
committerDiana Picus <diana.picus@linaro.org>2016-12-19 14:07:50 +0000
commit36aa09fa3c45038c832ccd952a6972f89922ea16 (patch)
tree423f242572d38303725be26fa5621ebad95abd31 /llvm/lib/Target
parentb6945e33017b01a60977a76cf816625398851234 (diff)
downloadbcm5719-llvm-36aa09fa3c45038c832ccd952a6972f89922ea16.tar.gz
bcm5719-llvm-36aa09fa3c45038c832ccd952a6972f89922ea16.zip
[ARM] GlobalISel: Select i8 and i16 copies
Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARMInstructionSelector.cpp11
1 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index c01043dddea..b17155a4791 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -42,8 +42,15 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
(void)RegBank;
assert(RegBank && "Can't get reg bank for virtual register");
- assert(MRI.getType(DstReg).getSizeInBits() ==
- RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI) &&
+ const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
+ unsigned SrcReg = I.getOperand(1).getReg();
+ const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
+ (void)SrcSize;
+ assert((DstSize == SrcSize ||
+ // Copies are a means to setup initial types, the number of
+ // bits may not exactly match.
+ (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
+ DstSize <= SrcSize)) &&
"Copy with different width?!");
assert(RegBank->getID() == ARM::GPRRegBankID && "Unsupported reg bank");
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