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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-05-02 19:26:14 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-05-02 19:26:14 +0000
commit350c22c587353f0d34cb585e49b512af10f03ed7 (patch)
treec6c62ac3d7625f06c0e7c8c1ef9f448d5c9d991c /llvm/lib/Target
parent1368e484e31f75ddf22bf68cbc7a8190a0f65cb5 (diff)
downloadbcm5719-llvm-350c22c587353f0d34cb585e49b512af10f03ed7.tar.gz
bcm5719-llvm-350c22c587353f0d34cb585e49b512af10f03ed7.zip
[X86][SNB] Fix scheduling of MMX integer multiply instructions.
The entries were being bound to the wrong class. llvm-svn: 331388
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td16
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 8923eb1fb38..cf15ccd77a3 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -1247,14 +1247,14 @@ def SBWriteResGroup89_2 : SchedWriteRes<[SBPort0,SBPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMADDUBSWrm",
- "MMX_PMADDWDirm",
- "MMX_PMULHRSWrm",
- "MMX_PMULHUWirm",
- "MMX_PMULHWirm",
- "MMX_PMULLWirm",
- "MMX_PMULUDQirm",
- "MMX_PSADBWirm")>;
+def: InstRW<[SBWriteResGroup89_2], (instregex "MMX_PMADDUBSWrm",
+ "MMX_PMADDWDirm",
+ "MMX_PMULHRSWrm",
+ "MMX_PMULHUWirm",
+ "MMX_PMULHWirm",
+ "MMX_PMULLWirm",
+ "MMX_PMULUDQirm",
+ "MMX_PSADBWirm")>;
def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 9;
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