diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-03 15:08:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-03 15:08:36 +0000 |
| commit | 344d68d3c9d3b85f41787f5120b22cf8180402be (patch) | |
| tree | 7ad3348be9a36e0fca5bacd25c2cdf034165b3bf /llvm/lib/Target | |
| parent | ada33314a298dc84636af8337eaa77d259d46fcf (diff) | |
| download | bcm5719-llvm-344d68d3c9d3b85f41787f5120b22cf8180402be.tar.gz bcm5719-llvm-344d68d3c9d3b85f41787f5120b22cf8180402be.zip | |
AMDGPU: Remove redundant patterns for shifts
llvm-svn: 359895
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP2Instructions.td | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td index 33b4cb774a5..3d7c75a3a04 100644 --- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -519,11 +519,9 @@ class DivergentClampingBinOp<SDPatternOperator Op, VOP_Pseudo Inst> : ) >; -let AddedComplexity = 1 in { - def : DivergentBinOp<srl, V_LSHRREV_B32_e64>; - def : DivergentBinOp<sra, V_ASHRREV_I32_e64>; - def : DivergentBinOp<shl, V_LSHLREV_B32_e64>; -} +def : DivergentBinOp<srl, V_LSHRREV_B32_e64>; +def : DivergentBinOp<sra, V_ASHRREV_I32_e64>; +def : DivergentBinOp<shl, V_LSHLREV_B32_e64>; let SubtargetPredicate = HasAddNoCarryInsts in { def : DivergentBinOp<add, V_ADD_U32_e32>; @@ -534,12 +532,9 @@ let SubtargetPredicate = isGFX6GFX7GFX8GFX9, Predicates = [isGFX6GFX7GFX8GFX9] i def : DivergentBinOp<add, V_ADD_I32_e32>; def : DivergentBinOp<sub, V_SUB_I32_e32>; -def : DivergentBinOp<srl, V_LSHRREV_B32_e32>; -def : DivergentBinOp<sra, V_ASHRREV_I32_e32>; -def : DivergentBinOp<shl, V_LSHLREV_B32_e32>; -} def : DivergentBinOp<adde, V_ADDC_U32_e32>; def : DivergentBinOp<sube, V_SUBB_U32_e32>; +} class divergent_i64_BinOp <SDPatternOperator Op, Instruction Inst> : GCNPat< |
