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| author | Eric Christopher <echristo@apple.com> | 2010-08-05 18:36:20 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2010-08-05 18:36:20 +0000 |
| commit | 32f5d6b9be7bffbbca6b8841d2913589c9b00b27 (patch) | |
| tree | 3324d2535300759303b5a335ed6863be4203ee3c /llvm/lib/Target | |
| parent | 4abffad17cd045f27f20b47eb2a9199bd5df5bad (diff) | |
| download | bcm5719-llvm-32f5d6b9be7bffbbca6b8841d2913589c9b00b27.tar.gz bcm5719-llvm-32f5d6b9be7bffbbca6b8841d2913589c9b00b27.zip | |
Be a little bit more specific about target for the memory barrier
instructions.
llvm-svn: 110360
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86Instr64bit.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td index 04b75f9f8bc..4e2710b2ee5 100644 --- a/llvm/lib/Target/X86/X86Instr64bit.td +++ b/llvm/lib/Target/X86/X86Instr64bit.td @@ -1624,7 +1624,8 @@ let Defs = [ESP] in def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero), "lock\n\t" "or{q}\t{$zero, (%rsp)|(%rsp), $zero}", - [(X86MemBarrierNoSSE GR64:$zero)]>, LOCK; + [(X86MemBarrierNoSSE GR64:$zero)]>, + Requires<[In64BitMode]>, LOCK; let Defs = [RAX, EFLAGS], Uses = [RAX] in { def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap), diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 5fc1bb7be1b..b0e6b651ce1 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -3938,7 +3938,8 @@ let Defs = [ESP] in def Int_MemBarrierNoSSE : I<0x09, MRM1r, (outs), (ins GR32:$zero), "lock\n\t" "or{l}\t{$zero, (%esp)|(%esp), $zero}", - [(X86MemBarrierNoSSE GR32:$zero)]>, LOCK; + [(X86MemBarrierNoSSE GR32:$zero)]>, + Requires<[In32BitMode]>, LOCK; } // Atomic swap. These are just normal xchg instructions. But since a memory |
