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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-22 21:37:08 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-22 21:37:08 +0000 |
| commit | 326594bc920bd15b19a713ef5dde404970c79b45 (patch) | |
| tree | adb0d26ced375bf8d2225b4cf185ab5ebd698717 /llvm/lib/Target | |
| parent | 578fe177d467bfbd0814de83814575111b493bda (diff) | |
| download | bcm5719-llvm-326594bc920bd15b19a713ef5dde404970c79b45.tar.gz bcm5719-llvm-326594bc920bd15b19a713ef5dde404970c79b45.zip | |
[X86][Znver1] Remove unnecessary BMI1 ANDN InstRW overrides.
llvm-svn: 330558
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index e0e89670067..1a2fcc4d79d 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -532,12 +532,6 @@ def : InstRW<[WriteALULd], (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>; -// ANDN. -// r,r. -def : InstRW<[WriteALU], (instregex "ANDN(32|64)rr")>; -// r,m. -def : InstRW<[WriteALULd, ReadAfterLd], (instregex "ANDN(32|64)rm")>; - // Define ALU latency variants def ZnWriteALULat2 : SchedWriteRes<[ZnALU]> { let Latency = 2; |
