AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor

llvm-svn: 373180

1 files changed, 17 insertions, 15 deletions

diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 0dda9687a15..e5f215fbcd7 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -777,6 +777,23 @@ class ZExt_i16_i1_Pat <SDNode ext> : GCNPat <
                      $src)
 >;
 
+foreach vt = [i16, v2i16] in {
+def : GCNPat <
+  (and vt:$src0, vt:$src1),
+  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
+>;
+
+def : GCNPat <
+  (or vt:$src0, vt:$src1),
+  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
+>;
+
+def : GCNPat <
+  (xor vt:$src0, vt:$src1),
+  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
+>;
+}
+
 let Predicates = [Has16BitInsts] in {
 
 let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
@@ -799,21 +816,6 @@ defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64,   1>;
 defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64,   1>;
 }
 
-def : GCNPat <
-  (and i16:$src0, i16:$src1),
-  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
->;
-
-def : GCNPat <
-  (or i16:$src0, i16:$src1),
-  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
->;
-
-def : GCNPat <
-  (xor i16:$src0, i16:$src1),
-  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
->;
-
 let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
 defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>;
 defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>;