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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2016-04-13 16:02:25 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2016-04-13 16:02:25 +0000 |
| commit | 2f6845ba3985b6758ae00615cdc307e55b4bcafc (patch) | |
| tree | 03dda658ed823a330954b0851cd0790b34be5412 /llvm/lib/Target | |
| parent | 3751d4114c8b5c8a0e78fb3d746123afc3758030 (diff) | |
| download | bcm5719-llvm-2f6845ba3985b6758ae00615cdc307e55b4bcafc.tar.gz bcm5719-llvm-2f6845ba3985b6758ae00615cdc307e55b4bcafc.zip | |
[mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointers correctly
Differential Revision: http://reviews.llvm.org/D18995
llvm-svn: 266204
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 37bb429f5f5..d82b87e5eef 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -1466,6 +1466,9 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, MachineFunction *MF = BB->getParent(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + bool ArePtrs64bit = ABI.ArePtrs64bit(); + const TargetRegisterClass *RCp = + getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); @@ -1474,7 +1477,7 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, unsigned CmpVal = MI->getOperand(2).getReg(); unsigned NewVal = MI->getOperand(3).getReg(); - unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); + unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); unsigned Mask = RegInfo.createVirtualRegister(RC); unsigned Mask2 = RegInfo.createVirtualRegister(RC); @@ -1482,7 +1485,7 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, unsigned OldVal = RegInfo.createVirtualRegister(RC); unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); - unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); + unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); unsigned MaskUpper = RegInfo.createVirtualRegister(RC); unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); @@ -1521,6 +1524,7 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, // addiu masklsb2,$0,-4 # 0xfffffffc // and alignedaddr,ptr,masklsb2 // andi ptrlsb2,ptr,3 + // xori ptrlsb2,ptrlsb2,3 # Only for BE // sll shiftamt,ptrlsb2,3 // ori maskupper,$0,255 # 0xff // sll mask,maskupper,shiftamt @@ -1530,11 +1534,12 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, // andi maskednewval,newval,255 // sll shiftednewval,maskednewval,shiftamt int64_t MaskImm = (Size == 1) ? 255 : 65535; - BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) - .addReg(Mips::ZERO).addImm(-4); - BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) + BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) + .addReg(ABI.GetNullPtr()).addImm(-4); + BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) .addReg(Ptr).addReg(MaskLSB2); - BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); + BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) + .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); if (Subtarget.isLittle()) { BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); } else { |
